From patchwork Mon Dec 4 18:37:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Tucker X-Patchwork-Id: 120578 Delivered-To: patch@linaro.org Received: by 10.80.152.193 with SMTP id j59csp1227045edb; Mon, 4 Dec 2017 10:38:53 -0800 (PST) X-Google-Smtp-Source: AGs4zMZZtZIerPdpwnPW1PT7c/NKo20IepdyDsAWLuLD0VnDs77vakwZes8BukyKMwLwNnRPwhC6 X-Received: by 10.98.104.194 with SMTP id d185mr20143538pfc.155.1512412732897; Mon, 04 Dec 2017 10:38:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512412732; cv=none; d=google.com; s=arc-20160816; b=gaYw5KRiaJUAoKrmakV6iL8chlNLKtxTm0lpICA/OowEqALFhPSLEZgFoXmU7Lx3lX vUiJI4y7gwfCZP/A0RVtduWxWeFL6CDNnhxZ0diXWE6Djko9ynM0dRWyEYFil0W47ZZO dYabH/Yh8LXmQECCxpN1Jz4zJE/asB+HVUb6y95ii/MVdTfCnJB04RlFp9iLY2v4JC79 OCF6rnDKB3Sfq8qfQSwnWBp5yKoMzSWePjy1vUdflt4dWcAyBN2ShmYQ7PgTWBh46zha huchxot2v6dSL7p8dwFyOFu3KAHg/AqvJM+Fzpd5HewQVikJv4L9joC115f37TmwbRnA chRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=1MvoFkssn53S7Ibl1TbcXeNVajQ7xSpKMsSxBni4WTA=; b=Dfzg1nZWTc2Z/zvUpt0+LvoVkMhRYS8dBUId/f8jvTgze0aWUdpL9wW2U/cpSt57iC OXL8PvVLpHbTdUtSAkRL+P9mafBqNfOR9SxdHQZbE8wmPolYTIL8rDlJCyRwF8dJVFis WGb/QzD+1YjWMafRqLD+HkuvvbKQRcm2u9LC5J3AXcOHpKBa9DtMgz8+sdw2EDQgLwRO wMf1qnbRUiECSnloE0WCDPXBYVNelBfoxgAm51sm3F5kquixkR+05e/ECf1n+buGXv52 8jI8+aydoArg76ssaX15W6J7iLGXKTzuJGU33RQTyOuAqSj8L2K3hNIzRCaWZEjPsnri 3JbA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c11si10685811pfh.68.2017.12.04.10.38.52; Mon, 04 Dec 2017 10:38:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752733AbdLDSiu (ORCPT + 28 others); Mon, 4 Dec 2017 13:38:50 -0500 Received: from bhuna.collabora.co.uk ([46.235.227.227]:52810 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752691AbdLDSin (ORCPT ); Mon, 4 Dec 2017 13:38:43 -0500 Received: from submarine.cbg.collabora.co.uk (unknown [IPv6:2a00:5f00:102:0:d0a5:4565:9830:3aaf]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: gtucker) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id 42A442702E1; Mon, 4 Dec 2017 18:38:42 +0000 (GMT) From: Guillaume Tucker To: Jonathan Hunter , David Airlie Cc: dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Guillaume Tucker , Thierry Reding Subject: [PATCH 2/2] drm/tegra: sor: Fix hang on tegra124 due to NULL clk_out Date: Mon, 4 Dec 2017 18:37:59 +0000 Message-Id: <79b4a60f1d624b16eaef06258318861d4407fecd.1512411775.git.guillaume.tucker@collabora.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When neither HDMI nor DP is supported such as on the tegra124, the sor->clk_out is not initialised and remains NULL. In this case, the parent clock can't be assigned to it so revert to the previous behaviour of assigning it to the main sor->clock instead. This fixes a kernel hang on tegra124. Fixes: e1335e2f0cfc ("drm/tegra: sor: Reimplement pad clock") Signed-off-by: Guillaume Tucker CC: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) -- 2.11.0 diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index b0a1dedac802..8d2e29c9ab2b 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -255,7 +255,7 @@ static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) clk_disable_unprepare(sor->clk); - err = clk_set_parent(sor->clk_out, parent); + err = clk_set_parent(sor->clk_out ? sor->clk_out : sor->clk, parent); if (err < 0) return err; @@ -2698,15 +2698,19 @@ static int tegra_sor_probe(struct platform_device *pdev) sor->clk_pad = NULL; } - /* - * The bootloader may have set up the SOR such that it's module clock - * is sourced by one of the display PLLs. However, that doesn't work - * without properly having set up other bits of the SOR. - */ - err = clk_set_parent(sor->clk_out, sor->clk_safe); - if (err < 0) { - dev_err(&pdev->dev, "failed to use safe clock: %d\n", err); - goto remove; + if (sor->clk_out) { + /* + * The bootloader may have set up the SOR such that its module + * clock is sourced by one of the display PLLs. However, that + * doesn't work without properly having set up other bits of + * the SOR. + */ + err = clk_set_parent(sor->clk_out, sor->clk_safe); + if (err < 0) { + dev_err(&pdev->dev, "failed to use safe clock: %d\n", + err); + goto remove; + } } platform_set_drvdata(pdev, sor);