From patchwork Wed Jun 1 10:34:15 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 69007 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp14848qge; Wed, 1 Jun 2016 03:34:48 -0700 (PDT) X-Received: by 10.98.100.83 with SMTP id y80mr7346470pfb.84.1464777288516; Wed, 01 Jun 2016 03:34:48 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i73si50349813pfa.222.2016.06.01.03.34.48; Wed, 01 Jun 2016 03:34:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752089AbcFAKeh (ORCPT + 30 others); Wed, 1 Jun 2016 06:34:37 -0400 Received: from mail-pf0-f173.google.com ([209.85.192.173]:36602 "EHLO mail-pf0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750697AbcFAKef (ORCPT ); Wed, 1 Jun 2016 06:34:35 -0400 Received: by mail-pf0-f173.google.com with SMTP id f144so12899278pfa.3 for ; Wed, 01 Jun 2016 03:34:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=gLg+Y9hGs1zS7HtiISRwu6gOBQ0pq86iaBBdiWwD9Mw=; b=K2r3T1KSnG4RWqjzpjUuD/+PBVeMl0wCqiuMboIrv/bN89/As/WHJ1W+ODPlMlbb1r QZ0tQBeTXSQBJHXhcOxBXSmtZlitOwiwB9p/7J5bhC5tH3WlQq2Hyze5Gq4wQTT5myn3 w8cNm2rrS9UGzo/8xWL08mZrw+wSwUMqNhukk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=gLg+Y9hGs1zS7HtiISRwu6gOBQ0pq86iaBBdiWwD9Mw=; b=eMTHCSnpWwNvoAo+M1hKQkLXGMW3WTvz1MbrOiPh8OBcd6qAByt2NhbLb0mcytlgNP 4BYkrLDBkOyoLKOG2CfzJQrqsbFMkiIRhom1PwbrFXOHJ7geX//DFUyImTj01OO/G1p5 wUwjNdsFNB58auUBbU7Ag3tN1c9it7X6XPlClHdmMv1BBY5lrYKiNsyU8oUp/BvbCFRa lYJeAGuab11v98F9Ogi3VnXfOlwIsBvSAbOIzo6i5JYnFpUuCNYCGs//t8MS4atkPyUe 57Z9zYKrvRgYEItM+xTNtJ/DgjsESiN+cXsYMeIoCy8VUMIutmTRVRDqJvpzv89qxZv9 jcpA== X-Gm-Message-State: ALyK8tIGEZ94piQS33Xz32sHD4APLcaFqgXW3Fz3ewWkD3TUYCcApTB0tFbX1BNCJ1STO9xk X-Received: by 10.98.66.149 with SMTP id h21mr7278996pfd.56.1464777274697; Wed, 01 Jun 2016 03:34:34 -0700 (PDT) Received: from localhost ([122.167.174.248]) by smtp.gmail.com with ESMTPSA id g195sm47073042pfb.7.2016.06.01.03.34.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Jun 2016 03:34:33 -0700 (PDT) From: Viresh Kumar To: Rafael Wysocki , Kukjin Kim , Krzysztof Kozlowski Cc: linaro-kernel@lists.linaro.org, linux-pm@vger.kernel.org, Viresh Kumar , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/8] ARM: s3c24xx: Sort cpufreq tables Date: Wed, 1 Jun 2016 16:04:15 +0530 Message-Id: <872a8b970ce7eabb06b988680eaf6b1154fe99fa.1464776797.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.7.1.410.g6faf27b In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some later changes in cpufreq core require these tables to be sorted based on ascending order of their frequencies. There was only one offender. Fix it and add comments over the arrays. Signed-off-by: Viresh Kumar --- arch/arm/mach-s3c24xx/pll-s3c2410.c | 3 ++- arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c | 1 + arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) -- 2.7.1.410.g6faf27b diff --git a/arch/arm/mach-s3c24xx/pll-s3c2410.c b/arch/arm/mach-s3c24xx/pll-s3c2410.c index 5e37d368594b..7ee4924a543d 100644 --- a/arch/arm/mach-s3c24xx/pll-s3c2410.c +++ b/arch/arm/mach-s3c24xx/pll-s3c2410.c @@ -32,11 +32,12 @@ #include #include +/* This array should be sorted in ascending order of the frequencies */ static struct cpufreq_frequency_table pll_vals_12MHz[] = { { .frequency = 34000000, .driver_data = PLLVAL(82, 2, 3), }, { .frequency = 45000000, .driver_data = PLLVAL(82, 1, 3), }, - { .frequency = 51000000, .driver_data = PLLVAL(161, 3, 3), }, { .frequency = 48000000, .driver_data = PLLVAL(120, 2, 3), }, + { .frequency = 51000000, .driver_data = PLLVAL(161, 3, 3), }, { .frequency = 56000000, .driver_data = PLLVAL(142, 2, 3), }, { .frequency = 68000000, .driver_data = PLLVAL(82, 2, 2), }, { .frequency = 79000000, .driver_data = PLLVAL(71, 1, 2), }, diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c index b355fca6cc2e..a3fbfed75e28 100644 --- a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c +++ b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c @@ -20,6 +20,7 @@ #include #include +/* This array should be sorted in ascending order of the frequencies */ static struct cpufreq_frequency_table s3c2440_plls_12[] = { { .frequency = 75000000, .driver_data = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */ { .frequency = 80000000, .driver_data = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */ diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c index be9a248b5ce9..bcff89fd9871 100644 --- a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c +++ b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c @@ -20,6 +20,7 @@ #include #include +/* This array should be sorted in ascending order of the frequencies */ static struct cpufreq_frequency_table s3c2440_plls_169344[] = { { .frequency = 78019200, .driver_data = PLLVAL(121, 5, 3), }, /* FVco 624.153600 */ { .frequency = 84067200, .driver_data = PLLVAL(131, 5, 3), }, /* FVco 672.537600 */