From patchwork Wed Apr 27 03:22:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 66765 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp1955835qge; Tue, 26 Apr 2016 20:24:09 -0700 (PDT) X-Received: by 10.98.72.199 with SMTP id q68mr8604678pfi.164.1461727449464; Tue, 26 Apr 2016 20:24:09 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n5si2609346pax.112.2016.04.26.20.24.09; Tue, 26 Apr 2016 20:24:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753044AbcD0DX5 (ORCPT + 29 others); Tue, 26 Apr 2016 23:23:57 -0400 Received: from mail-pa0-f47.google.com ([209.85.220.47]:36323 "EHLO mail-pa0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753028AbcD0DXy (ORCPT ); Tue, 26 Apr 2016 23:23:54 -0400 Received: by mail-pa0-f47.google.com with SMTP id bt5so13973452pac.3 for ; Tue, 26 Apr 2016 20:23:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=pIzKnYZsLExtxqiOKt/FJEfmqnrWWOPXng5EDI2Ja7A=; b=PPD5y0ZfYKJ7v5IuKuKXuHUbbwwB4twZNIwU41kVfdg0K+Q5/ta08V1Vg2TY98DSDu JIK9Rdxzm5+T7PTgf+8zjGz358eTsPQOTxHrR5a52jdYPNLXR0Uaup+R/6EsfhJfytSe 9PtOzXod2U9BwV5OBGKpr9lrBKa5CzmoOyAqQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=pIzKnYZsLExtxqiOKt/FJEfmqnrWWOPXng5EDI2Ja7A=; b=goduco57hb0/C8b+Ww2CO5+pFH8xG+y416KFO2A6JYqrkqczbG4zQrybCSsY6O9YUx TebkQp9FV0j8KoU4APTppghftghIdnK0pbXknPArctPeVeUKdBfDOIO/oYBWrYTX0+5V +NRehXvwG2KuUyejkUJyuvRP0QfZaU1KN7PROzEoeH2u9CZT/DalTJ9G6QTnrgtberZr aqz3EjOfoIIRZh3zO636Gu2gNXrYFxTk+y0K+dN4MxOuywWxBDwZq+N+bjoFk2IIh4GU YsmBtnVIa3KESToc+0MpXxQuYm7hTKlHaNUQIWLnrnU1HHLA4BV93fn+aSiWhDJ1A+8u ICaQ== X-Gm-Message-State: AOPr4FXfW9M+NtvwsuGg1Y1Cl2RlXxgH8WgH9td6Wg7TTXe+YlPJBrrG5mKIAxsrtpKzkj17 X-Received: by 10.66.88.104 with SMTP id bf8mr8584360pab.129.1461727433281; Tue, 26 Apr 2016 20:23:53 -0700 (PDT) Received: from localhost ([122.167.143.140]) by smtp.gmail.com with ESMTPSA id u2sm1957993pan.45.2016.04.26.20.23.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 Apr 2016 20:23:52 -0700 (PDT) From: Viresh Kumar To: Rafael Wysocki , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Viresh Kumar Cc: linaro-kernel@lists.linaro.org, linux-pm@vger.kernel.org, nm@ti.com, sboyd@codeaurora.org, arnd.bergmann@linaro.org, Thomas Petazzoni , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH V2 7/7] cpufreq: mvebu: Move cpufreq code into drivers/cpufreq/ Date: Wed, 27 Apr 2016 08:52:27 +0530 Message-Id: <8bac5a9dfb9280051d9f5dc3773106c253ad16d2.1461727086.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.7.1.410.g6faf27b In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Move cpufreq bits for mvebu into drivers/cpufreq/ directory, that's where they really belong to. Compiled tested only. Cc: Thomas Petazzoni Cc: Jason Cooper Cc: Andrew Lunn Cc: Gregory Clement Cc: Sebastian Hesselbarth Signed-off-by: Viresh Kumar --- MAINTAINERS | 1 + arch/arm/mach-mvebu/pmsu.c | 85 ------------------------------- drivers/cpufreq/Makefile | 1 + drivers/cpufreq/mvebu-cpufreq.c | 107 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 109 insertions(+), 85 deletions(-) create mode 100644 drivers/cpufreq/mvebu-cpufreq.c -- 2.7.1.410.g6faf27b diff --git a/MAINTAINERS b/MAINTAINERS index 1d5b4becab6f..0bb566e7df9b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1322,6 +1322,7 @@ F: drivers/rtc/rtc-armada38x.c F: arch/arm/boot/dts/armada* F: arch/arm/boot/dts/kirkwood* F: arch/arm64/boot/dts/marvell/armada* +F: drivers/cpufreq/mvebu-cpufreq.c ARM/Marvell Berlin SoC support diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c index 8928f7caaf70..b44442338e4e 100644 --- a/arch/arm/mach-mvebu/pmsu.c +++ b/arch/arm/mach-mvebu/pmsu.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -607,87 +606,3 @@ int mvebu_pmsu_dfs_request(int cpu) return 0; } - -static int __init armada_xp_pmsu_cpufreq_init(void) -{ - struct device_node *np; - struct resource res; - int ret, cpu; - - if (!of_machine_is_compatible("marvell,armadaxp")) - return 0; - - /* - * In order to have proper cpufreq handling, we need to ensure - * that the Device Tree description of the CPU clock includes - * the definition of the PMU DFS registers. If not, we do not - * register the clock notifier and the cpufreq driver. This - * piece of code is only for compatibility with old Device - * Trees. - */ - np = of_find_compatible_node(NULL, NULL, "marvell,armada-xp-cpu-clock"); - if (!np) - return 0; - - ret = of_address_to_resource(np, 1, &res); - if (ret) { - pr_warn(FW_WARN "not enabling cpufreq, deprecated armada-xp-cpu-clock binding\n"); - of_node_put(np); - return 0; - } - - of_node_put(np); - - /* - * For each CPU, this loop registers the operating points - * supported (which are the nominal CPU frequency and half of - * it), and registers the clock notifier that will take care - * of doing the PMSU part of a frequency transition. - */ - for_each_possible_cpu(cpu) { - struct device *cpu_dev; - struct clk *clk; - int ret; - - cpu_dev = get_cpu_device(cpu); - if (!cpu_dev) { - pr_err("Cannot get CPU %d\n", cpu); - continue; - } - - clk = clk_get(cpu_dev, 0); - if (IS_ERR(clk)) { - pr_err("Cannot get clock for CPU %d\n", cpu); - return PTR_ERR(clk); - } - - /* - * In case of a failure of dev_pm_opp_add(), we don't - * bother with cleaning up the registered OPP (there's - * no function to do so), and simply cancel the - * registration of the cpufreq device. - */ - ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk), 0); - if (ret) { - clk_put(clk); - return ret; - } - - ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk) / 2, 0); - if (ret) { - clk_put(clk); - return ret; - } - - ret = dev_pm_opp_set_sharing_cpus(cpu_dev, - cpumask_of(cpu_dev->id)); - if (ret) - dev_err(cpu_dev, "%s: failed to mark OPPs as shared: %d\n", - __func__, ret); - } - - platform_device_register_simple("cpufreq-dt", -1, NULL, 0); - return 0; -} - -device_initcall(armada_xp_pmsu_cpufreq_init); diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 2cce2cd400f9..e1eb11ee3570 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -79,6 +79,7 @@ obj-$(CONFIG_ARM_TEGRA20_CPUFREQ) += tegra20-cpufreq.o obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) += tegra124-cpufreq.o obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o obj-$(CONFIG_ACPI_CPPC_CPUFREQ) += cppc_cpufreq.o +obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o ################################################################################## diff --git a/drivers/cpufreq/mvebu-cpufreq.c b/drivers/cpufreq/mvebu-cpufreq.c new file mode 100644 index 000000000000..e920889b9ac2 --- /dev/null +++ b/drivers/cpufreq/mvebu-cpufreq.c @@ -0,0 +1,107 @@ +/* + * CPUFreq support for Armada 370/XP platforms. + * + * Copyright (C) 2012-2016 Marvell + * + * Yehuda Yitschak + * Gregory Clement + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define pr_fmt(fmt) "mvebu-pmsu: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include + +static int __init armada_xp_pmsu_cpufreq_init(void) +{ + struct device_node *np; + struct resource res; + int ret, cpu; + + if (!of_machine_is_compatible("marvell,armadaxp")) + return 0; + + /* + * In order to have proper cpufreq handling, we need to ensure + * that the Device Tree description of the CPU clock includes + * the definition of the PMU DFS registers. If not, we do not + * register the clock notifier and the cpufreq driver. This + * piece of code is only for compatibility with old Device + * Trees. + */ + np = of_find_compatible_node(NULL, NULL, "marvell,armada-xp-cpu-clock"); + if (!np) + return 0; + + ret = of_address_to_resource(np, 1, &res); + if (ret) { + pr_warn(FW_WARN "not enabling cpufreq, deprecated armada-xp-cpu-clock binding\n"); + of_node_put(np); + return 0; + } + + of_node_put(np); + + /* + * For each CPU, this loop registers the operating points + * supported (which are the nominal CPU frequency and half of + * it), and registers the clock notifier that will take care + * of doing the PMSU part of a frequency transition. + */ + for_each_possible_cpu(cpu) { + struct device *cpu_dev; + struct clk *clk; + int ret; + + cpu_dev = get_cpu_device(cpu); + if (!cpu_dev) { + pr_err("Cannot get CPU %d\n", cpu); + continue; + } + + clk = clk_get(cpu_dev, 0); + if (IS_ERR(clk)) { + pr_err("Cannot get clock for CPU %d\n", cpu); + return PTR_ERR(clk); + } + + /* + * In case of a failure of dev_pm_opp_add(), we don't + * bother with cleaning up the registered OPP (there's + * no function to do so), and simply cancel the + * registration of the cpufreq device. + */ + ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk), 0); + if (ret) { + clk_put(clk); + return ret; + } + + ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk) / 2, 0); + if (ret) { + clk_put(clk); + return ret; + } + + ret = dev_pm_opp_set_sharing_cpus(cpu_dev, + cpumask_of(cpu_dev->id)); + if (ret) + dev_err(cpu_dev, "%s: failed to mark OPPs as shared: %d\n", + __func__, ret); + } + + platform_device_register_simple("cpufreq-dt", -1, NULL, 0); + return 0; +} +device_initcall(armada_xp_pmsu_cpufreq_init);