From patchwork Tue Jun 5 04:47:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 137666 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp491447lji; Mon, 4 Jun 2018 21:57:02 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJIazgHAH7gfAYCQFQidpw4RVygtsn3PrG/HAr8zg5NY54DNNgdO/wpkza+trEOLVC3sUSD X-Received: by 2002:a65:4502:: with SMTP id n2-v6mr19045112pgq.95.1528174622185; Mon, 04 Jun 2018 21:57:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528174622; cv=none; d=google.com; s=arc-20160816; b=NgA9BlxEylpns/k6Ans4//WEFBuamYXRFSRF46+aN8QcF/aOYejB6tt/dbYoQvsNiH gKthfDAbxwBABwtUhElmKvpJoLFKiDVEQ1qDBubPp4Eieaxfv3fY1Xmv3ONYwYHM+JU2 coiPY+supSfFbXF5r0Y+uAfOtECJjglMcyUQk1ZC+NyVZxd9jLjKz4CtNOV+GyPZziGR ivzadh8isOhEyCz3bvVQfXMen0tCvpPCwj3TRkqfLPs2CESP43xdXt8onKjXlc4Nl0PJ eD9+txcxCfukCDdYOZmetVQT3Pd+AbqwTCiLsxU71Je2i0U62aOI+fjLTTL0+/OZcWyg yayQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=EK5+HMcPGyH+d85nITsGfzrFtzmVetc0ClcpmeTtERY=; b=FX0a4BlUqiYGgODASvmRarao2TSXhADxi4xsFBNCos6M/985O7dZBdCTJG5PEzB4l0 vvB/O1xDmPSu1/QTLaTjqtOSLfo9MWpLP0xVoTx1U+7x05Uc/S2bI2Efy4NRoqzmQhrG KD/ZI0fc3IsKZlNE3F6L6m1v8LLmOADxcB/clEkUb/WB94myPPqZRgWClH362lXsRLbd ynJgqw86ANHoRJ2hE0AYnmleHgBtopJ+km2krdDQWj90dFX/0QCkNMzgMvCW+3kXD/kc Xc6hGllaiFvZokVkEk949Sm7yqHyaldNmZsaoqqTfE3dXJgNrhFmxJyz7VxC7AZQygdF 7g3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=C8fDGBcp; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y17-v6si31971371plp.485.2018.06.04.21.57.01; Mon, 04 Jun 2018 21:57:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=C8fDGBcp; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751589AbeFEE47 (ORCPT + 30 others); Tue, 5 Jun 2018 00:56:59 -0400 Received: from mail-pl0-f66.google.com ([209.85.160.66]:33132 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751542AbeFEE44 (ORCPT ); Tue, 5 Jun 2018 00:56:56 -0400 Received: by mail-pl0-f66.google.com with SMTP id n10-v6so747187plp.0 for ; Mon, 04 Jun 2018 21:56:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EK5+HMcPGyH+d85nITsGfzrFtzmVetc0ClcpmeTtERY=; b=C8fDGBcph1nnli3l5E4ss8NZpEnZ+Fmqrg2X1aVGJRSoRrI5ecw9K7IpSWSL+M4kn1 WFGRJ9Dfw2lDSyDvVzS2rzxlQcZTRNhAb621CW+f9kXK93JQn4YBO8MitMn1VRAgJPNu x7fgohdi2ryV8gy6KIwBu1qmzaLgiXTcX+E60= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EK5+HMcPGyH+d85nITsGfzrFtzmVetc0ClcpmeTtERY=; b=QCN8NkCN4EUPdm8ZAt9sx+SnEUymS2SvLBLxGhdYhGqzbKoqR3+Pm1BvJz7RfDfwQt f6T/2LLd7d237DIw9dp3ln2yacOt5jXgsn/SSGRKsAEUlGim3Qunx9t1KHtV2HomWdZB fznsyVBUQQsFP46EYpZYvl+xG5E8ZMmV2AI0lqSWJq1TU6o736prHngF3EZLtMqOXnrI /aXsC6K5eMOHSekh2Nku+mGeuWJUZ00LINWUeCSI7BLvRoCPW5WqgQy3yKPhplv87RPW z0Bd525I8YerNKhkqTT4q86MfUB8mDR9mRC7xVsAItbYGnK1pNtD0xC1ORiOQxc9Hd+v Kpqw== X-Gm-Message-State: ALKqPwemeCMgklLh/zrtLIBRuy1ZGCvcodfUcKBMqL/HSbn9JS16+6ll VfhdHTxl7p02E7djjaFrlg9PdQ== X-Received: by 2002:a17:902:b217:: with SMTP id t23-v6mr15893505plr.312.1528174615158; Mon, 04 Jun 2018 21:56:55 -0700 (PDT) Received: from localhost ([122.172.63.23]) by smtp.gmail.com with ESMTPSA id y20-v6sm36317804pge.46.2018.06.04.21.56.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jun 2018 21:56:54 -0700 (PDT) From: Viresh Kumar To: arm@kernel.org, Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai Cc: Viresh Kumar , Vincent Guittot , ionela.voinescu@arm.com, Daniel Lezcano , chris.redpath@arm.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 2/2] arm: dts: sunxi: Add missing cooling device properties for CPUs Date: Tue, 5 Jun 2018 10:17:49 +0530 Message-Id: X-Mailer: git-send-email 2.15.0.194.g9af6a3dea062 In-Reply-To: References: <20180601151701.sshwfdbflic6mybv@flea> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Fix other missing properties (clocks, OPP, clock latency) as well to make it all work. Signed-off-by: Viresh Kumar --- V2: - Separated patch for h3 - Fixed subject s/sun/sunxi/ arch/arm/boot/dts/sun6i-a31.dtsi | 30 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/sun7i-a20.dtsi | 13 +++++++++++++ arch/arm/boot/dts/sun8i-a33.dtsi | 9 +++++++++ 3 files changed, 52 insertions(+) -- 2.15.0.194.g9af6a3dea062 diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index c72992556a86..debc0bf22ea3 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -119,18 +119,48 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 1008000 1200000 + 864000 1200000 + 720000 1100000 + 480000 1000000 + >; + #cooling-cells = <2>; }; cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 1008000 1200000 + 864000 1200000 + 720000 1100000 + 480000 1000000 + >; + #cooling-cells = <2>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 1008000 1200000 + 864000 1200000 + 720000 1100000 + 480000 1000000 + >; + #cooling-cells = <2>; }; }; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index e529e4ff2174..35372a0cfc8d 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -122,6 +122,19 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 960000 1400000 + 912000 1400000 + 864000 1300000 + 720000 1200000 + 528000 1100000 + 312000 1000000 + 144000 1000000 + >; + #cooling-cells = <2>; }; }; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 8d278ee001e9..4e92741b24a7 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -132,21 +132,30 @@ }; cpu@1 { + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; };