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[209.132.180.67]) by mx.google.com with ESMTP id z10si2359910pgp.671.2018.01.09.19.48.31; Tue, 09 Jan 2018 19:48:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gkxrNxuB; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965247AbeAJDs0 (ORCPT + 28 others); Tue, 9 Jan 2018 22:48:26 -0500 Received: from mail-pg0-f66.google.com ([74.125.83.66]:43942 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965232AbeAJDsW (ORCPT ); Tue, 9 Jan 2018 22:48:22 -0500 Received: by mail-pg0-f66.google.com with SMTP id f14so7238597pga.10 for ; Tue, 09 Jan 2018 19:48:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=SjXMPtCgr7kmgW6Sc3OPuAZH24KsIrVGddQxvD6R5y0=; b=gkxrNxuBaAWUumc3op6iTOkXIZQQv2Jeuq7jO3YUNfPbGp2FabzyyRQlGILvchZruz M1oPtBLmrsT8pO8FDv3us0UniqhX9Bm/How2LTSuOc2r6IZSw7oKDaddqtEzJpqI8OkY MuCUVOoIKJ7U5D3hn9WmbxNpHyIgctRSwfcZw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=SjXMPtCgr7kmgW6Sc3OPuAZH24KsIrVGddQxvD6R5y0=; b=KRQsjVVy5eaeAqbwUd6ttqCVlSSOZf5Jd7zqF++uv8Ov1s8b2JYjJvcN1eK85qTq6E s5R3T8yMPTKxZ0/jM9trbCf9nqBXQuO9AkkNvO3ceGSl6AOWl2FmDxmO+s5EFD4qV43o cJgJpcbA+VG6BEjxmvRq2p58Ljpv8zA/kxqHAFhTgjuzX4F1AMqCmrR/bm7/KmKwzhqF Qi6mUV0Hz1FA9lEKiA7LG/Zl9Q3haLyeHa+RVqpIOJYDr7u/D4IlQVpAfZDVNWO0kXEB Zrp1BT+bS1L0XXPAm6jfAHKdLsGfYbicmIwIzm+VgZQBFW1SXTL3U7vYqA08LYnSFJQR fzTg== X-Gm-Message-State: AKGB3mIWKugeu4QpVwIFc6aK7t/QAcyRGvOiYyAgxIjv/sXcNggsxHFj J6pAaEhcNsd+DPh3ZR/fDjEe0w== X-Received: by 10.98.68.135 with SMTP id m7mr15604341pfi.9.1515556101832; Tue, 09 Jan 2018 19:48:21 -0800 (PST) Received: from localhost ([122.172.19.39]) by smtp.gmail.com with ESMTPSA id d24sm5769069pfb.30.2018.01.09.19.48.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Jan 2018 19:48:21 -0800 (PST) From: Viresh Kumar To: Greg Kroah-Hartman Cc: Viresh Kumar , Vincent Guittot , Stephen Boyd , Rajendra Nayak , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, robdclark@gmail.com, s.hauer@pengutronix.de, l.stach@pengutronix.de, shawnguo@kernel.org, fabio.estevam@nxp.com, nm@ti.com, xuwei5@hisilicon.com, robh+dt@kernel.org Subject: [PATCH V6 11/13] boot_constraint: Add Qualcomm display controller constraints Date: Wed, 10 Jan 2018 09:17:40 +0530 Message-Id: X-Mailer: git-send-email 2.15.0.194.g9af6a3dea062 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Rajendra Nayak This sets boot constraints for the display controller used on Qualcomm dragonboard 410c. The display controlled is enabled by the bootloader to show a flash screen during kernel boot. The handover to kernel should be without any glitches on the screen.The resources of the display controller (like regulators) are shared with other peripherals, which may reconfigure those resources before the display driver comes up. The same problem can happen if the display driver probes first, as the constraints of the other devices (sharing same resources with display controller) may not be honored anymore by the kernel. Signed-off-by: Rajendra Nayak Signed-off-by: Viresh Kumar --- arch/arm64/Kconfig.platforms | 1 + drivers/boot_constraint/Makefile | 1 + drivers/boot_constraint/qcom.c | 122 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 124 insertions(+) create mode 100644 drivers/boot_constraint/qcom.c -- 2.15.0.194.g9af6a3dea062 diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index a586ed728393..b514327290ca 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -136,6 +136,7 @@ config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB select PINCTRL + select DEV_BOOT_CONSTRAINT help This enables support for the ARMv8 based Qualcomm chipsets. diff --git a/drivers/boot_constraint/Makefile b/drivers/boot_constraint/Makefile index f3e123b5d854..7b6b5966c908 100644 --- a/drivers/boot_constraint/Makefile +++ b/drivers/boot_constraint/Makefile @@ -4,3 +4,4 @@ obj-y := clk.o deferrable_dev.o core.o pm.o supply.o obj-$(CONFIG_ARCH_HISI) += hikey.o obj-$(CONFIG_ARCH_MXC) += imx.o +obj-$(CONFIG_ARCH_QCOM) += qcom.o diff --git a/drivers/boot_constraint/qcom.c b/drivers/boot_constraint/qcom.c new file mode 100644 index 000000000000..0498f464da05 --- /dev/null +++ b/drivers/boot_constraint/qcom.c @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This sets up Dragonboard 410c constraints on behalf of the bootloader, which + * uses display controller to display a flash screen during system boot. + * + * Copyright (C) 2017 Linaro. + * Viresh Kumar + * Rajendra Nayak + */ + +#include +#include +#include +#include + +static struct dev_boot_constraint_clk_info iface_clk_info = { + .name = "iface_clk", +}; + +static struct dev_boot_constraint_clk_info bus_clk_info = { + .name = "bus_clk", +}; + +static struct dev_boot_constraint_clk_info core_clk_info = { + .name = "core_clk", +}; + +static struct dev_boot_constraint_clk_info vsync_clk_info = { + .name = "vsync_clk", +}; + +static struct dev_boot_constraint_clk_info esc0_clk_info = { + .name = "core_clk", +}; + +static struct dev_boot_constraint_clk_info byte_clk_info = { + .name = "byte_clk", +}; + +static struct dev_boot_constraint_clk_info pixel_clk_info = { + .name = "pixel_clk", +}; + +static struct dev_boot_constraint_supply_info vdda_info = { + .name = "vdda" +}; + +static struct dev_boot_constraint_supply_info vddio_info = { + .name = "vddio" +}; + +static struct dev_boot_constraint constraints_mdss[] = { + { + .type = DEV_BOOT_CONSTRAINT_PM, + .data = NULL, + }, +}; + +static struct dev_boot_constraint constraints_mdp[] = { + { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &iface_clk_info, + }, { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &bus_clk_info, + }, { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &core_clk_info, + }, { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &vsync_clk_info, + }, +}; + +static struct dev_boot_constraint constraints_dsi[] = { + { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &esc0_clk_info, + }, { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &byte_clk_info, + }, { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &pixel_clk_info, + }, { + .type = DEV_BOOT_CONSTRAINT_SUPPLY, + .data = &vdda_info, + + }, { + .type = DEV_BOOT_CONSTRAINT_SUPPLY, + .data = &vddio_info, + }, +}; + +static struct dev_boot_constraint_of constraints[] = { + { + .compat = "qcom,mdss", + .constraints = constraints_mdss, + .count = ARRAY_SIZE(constraints_mdss), + }, { + .compat = "qcom,mdp5", + .constraints = constraints_mdp, + .count = ARRAY_SIZE(constraints_mdp), + }, { + .compat = "qcom,mdss-dsi-ctrl", + .constraints = constraints_dsi, + .count = ARRAY_SIZE(constraints_dsi), + }, +}; + +static int __init qcom_constraints_init(void) +{ + /* Only Dragonboard 410c is supported for now */ + if (!of_machine_is_compatible("qcom,apq8016-sbc")) + return 0; + + dev_boot_constraint_add_deferrable_of(constraints, + ARRAY_SIZE(constraints)); + + return 0; +} +subsys_initcall(qcom_constraints_init);