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[209.132.180.67]) by mx.google.com with ESMTP id v9si6035897pgt.770.2017.10.09.13.23.58; Mon, 09 Oct 2017 13:23:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755309AbdJIUX3 (ORCPT + 26 others); Mon, 9 Oct 2017 16:23:29 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:43682 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754681AbdJIUXA (ORCPT ); Mon, 9 Oct 2017 16:23:00 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id BCFDA20924; Mon, 9 Oct 2017 22:22:57 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (LFbn-TOU-1-209-191.w86-201.abo.wanadoo.fr [86.201.56.191]) by mail.free-electrons.com (Postfix) with ESMTPSA id 97BBA2083E; Mon, 9 Oct 2017 22:22:57 +0200 (CEST) From: Maxime Ripard To: Chen-Yu Tsai , Maxime Ripard , Mark Rutland , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] ARM: dts: sun9i: Change node names to remove underscores Date: Mon, 9 Oct 2017 22:22:53 +0200 Message-Id: X-Mailer: git-send-email 2.13.6 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some node names in the A80 DTSI still have underscores in them. Remove them in favour of hyphens to remove DTC warnings. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- git-series 0.9.1 diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index f9cb701f29b0..90eac0b2a193 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -139,7 +139,7 @@ * would also throw all the PLL clock rates off, or just the * downstream clocks in the PRCM. */ - osc24M: osc24M_clk { + osc24M: clk-24M { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -151,7 +151,7 @@ * AC100 codec/RTC chip. This serves as a placeholder for * board dts files to specify the source. */ - osc32k: osc32k_clk { + osc32k: clk-32k { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <1>; @@ -169,7 +169,7 @@ clock-output-names = "cpus"; }; - ahbs: ahbs_clk { + ahbs: clk-ahbs { compatible = "fixed-factor-clock"; #clock-cells = <0>; clock-div = <1>; @@ -708,12 +708,12 @@ #interrupt-cells = <3>; #gpio-cells = <3>; - r_ir_pins: r_ir { + r_ir_pins: r-ir-pins { pins = "PL6"; function = "s_cir_rx"; }; - r_rsb_pins: r_rsb { + r_rsb_pins: r-rsb-pins { pins = "PN0", "PN1"; function = "s_rsb"; drive-strength = <20>;