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[83.233.90.46]) by smtp.gmail.com with ESMTPSA id l204sm2085534lfg.49.2016.01.08.11.32.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jan 2016 11:32:01 -0800 (PST) From: Christophe Milard To: anders.roxell@linaro.org, mike.holmes@linaro.org, stuart.haslam@linaro.org, maxim.uvarov@linaro.org, bill.fischofer@linaro.org, petri.savolainen@linaro.org, edavis@broadcom.com Date: Fri, 8 Jan 2016 21:30:06 +0100 Message-Id: <1452285014-60320-24-git-send-email-christophe.milard@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1452285014-60320-1-git-send-email-christophe.milard@linaro.org> References: <1452285014-60320-1-git-send-email-christophe.milard@linaro.org> Cc: lng-odp@lists.linaro.org Subject: [lng-odp] [API-NEXT RFC 23/31] drivers: ixgbe: fixing base/ixgbe_osdep.h for ODP X-BeenThere: lng-odp@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "The OpenDataPlane \(ODP\) List" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: lng-odp-bounces@lists.linaro.org Sender: "lng-odp" Signed-off-by: Christophe Milard --- drivers/ixgbe/base/ixgbe_osdep.h | 77 +++++++++++++++++++++++----------------- 1 file changed, 45 insertions(+), 32 deletions(-) diff --git a/drivers/ixgbe/base/ixgbe_osdep.h b/drivers/ixgbe/base/ixgbe_osdep.h index 40b0b51..cd30c18 100644 --- a/drivers/ixgbe/base/ixgbe_osdep.h +++ b/drivers/ixgbe/base/ixgbe_osdep.h @@ -30,32 +30,28 @@ POSSIBILITY OF SUCH DAMAGE. ******************************************************************************/ -/*$FreeBSD$*/ + #ifndef _IXGBE_OS_H_ #define _IXGBE_OS_H_ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../ixgbe_logs.h" -#include "../ixgbe_bypass_defines.h" +#include +#include "../../driver_log.h" -#define ASSERT(x) if(!(x)) rte_panic("IXGBE: x") +#define ASSERT(x) if (!(x)) DRV_ABORT("IXGBE:" #x) -#define DELAY(x) rte_delay_us(x) +#define DELAY(x) odp_time_wait_ns((x) * 1000) #define usec_delay(x) DELAY(x) -#define msec_delay(x) DELAY(1000*(x)) +#define msec_delay(x) DELAY(1000 * (x)) + +#ifdef IXGBE_DBG_BASE +#define DEBUGFUNC(F) DRV_DBG(F "\n") +#define DEBUGOUT(S, args...) DRV_DBG(S, ##args) +#else +#define DEBUGFUNC(F) +#define DEBUGOUT(S, args...) +#endif -#define DEBUGFUNC(F) DEBUGOUT(F "\n"); -#define DEBUGOUT(S, args...) PMD_DRV_LOG_RAW(DEBUG, S, ##args) #define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args) #define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args) #define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args) @@ -71,7 +67,12 @@ #define false 0 #define true 1 -#define min(a,b) RTE_MIN(a,b) +#define min(a, b) ({ \ + __typeof__(a) _a = (a); \ + __typeof__(b) _b = (b); \ + _a < _b ? _a : _b; \ + }) + #define EWARN(hw, S, args...) DEBUGOUT1(S, ##args) @@ -93,12 +94,25 @@ enum { }; #define STATIC static -#define IXGBE_NTOHL(_i) rte_be_to_cpu_32(_i) -#define IXGBE_NTOHS(_i) rte_be_to_cpu_16(_i) -#define IXGBE_CPU_TO_LE32(_i) rte_cpu_to_le_32(_i) -#define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i) -#define IXGBE_CPU_TO_BE16(_i) rte_cpu_to_be_16(_i) -#define IXGBE_CPU_TO_BE32(_i) rte_cpu_to_be_32(_i) +#define IXGBE_NTOHL(_i) ntohl(_i) +#define IXGBE_NTOHS(_i) ntohs(_i) + +#define IXGBE_CPU_TO_BE16(_i) odp_cpu_to_be_16(_i) +#define IXGBE_BE16_TO_CPU(_i) odp_be_to_cpu_16(_i) +#define IXGBE_CPU_TO_LE16(_i) odp_cpu_to_le_16(_i) +#define IXGBE_LE16_TO_CPU(_i) odp_le_to_cpu_16(_i) + +#define IXGBE_CPU_TO_BE32(_i) odp_cpu_to_be_32(_i) +#define IXGBE_BE32_TO_CPU(_i) odp_be_to_cpu_32(_i) +#define IXGBE_CPU_TO_LE32(_i) odp_cpu_to_le_32(_i) +#define IXGBE_LE32_TO_CPU(_i) odp_le_to_cpu_32(_i) + +#define IXGBE_CPU_TO_BE64(_i) odp_cpu_to_be_64(_i) +#define IXGBE_BE64_TO_CPU(_i) odp_be_to_cpu_64(_i) +#define IXGBE_CPU_TO_LE64(_i) odp_cpu_to_le_64(_i) +#define IXGBE_LE64_TO_CPU(_i) odp_le_to_cpu_64(_i) + +#define IXGBE_LE32_TO_CPUS(x) IXGBE_LE32_TO_CPU(x) typedef uint8_t u8; typedef int8_t s8; @@ -107,25 +121,24 @@ typedef int16_t s16; typedef uint32_t u32; typedef int32_t s32; typedef uint64_t u64; -typedef int bool; -#define mb() rte_mb() -#define wmb() rte_wmb() -#define rmb() rte_rmb() +#define mb() odp_mb_full() /* full memory barrier */ +#define wmb() odp_mb_full() /* write memory barrier */ +#define rmb() odp_mb_full() /* read memory barrier */ #define IOMEM -#define prefetch(x) rte_prefetch0(x) +#define prefetch(x) #define IXGBE_PCI_REG(reg) (*((volatile uint32_t *)(reg))) static inline uint32_t ixgbe_read_addr(volatile void* addr) { - return rte_le_to_cpu_32(IXGBE_PCI_REG(addr)); + return IXGBE_LE32_TO_CPU(IXGBE_PCI_REG(addr)); } #define IXGBE_PCI_REG_WRITE(reg, value) do { \ - IXGBE_PCI_REG((reg)) = (rte_cpu_to_le_32(value)); \ + IXGBE_PCI_REG((reg)) = (IXGBE_CPU_TO_LE32(value)); \ } while(0) #define IXGBE_PCI_REG_ADDR(hw, reg) \