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[54.225.227.206]) by mx.google.com with ESMTP id p16si2157832qtb.121.2017.07.12.06.05.41; Wed, 12 Jul 2017 06:05:42 -0700 (PDT) Received-SPF: pass (google.com: domain of lng-odp-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of lng-odp-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=lng-odp-bounces@lists.linaro.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=yandex.ru Received: by lists.linaro.org (Postfix, from userid 109) id 91ACA608E2; Wed, 12 Jul 2017 13:05:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,FREEMAIL_FROM, RCVD_IN_DNSWL_LOW,URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 0FAB860725; Wed, 12 Jul 2017 13:02:03 +0000 (UTC) X-Original-To: lng-odp@lists.linaro.org Delivered-To: lng-odp@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 32F14644A2; Wed, 12 Jul 2017 13:01:57 +0000 (UTC) Received: from forward5j.cmail.yandex.net (forward5j.cmail.yandex.net [5.255.227.23]) by lists.linaro.org (Postfix) with ESMTPS id 6655A6064A for ; Wed, 12 Jul 2017 13:00:16 +0000 (UTC) Received: from smtp3o.mail.yandex.net (smtp3o.mail.yandex.net [IPv6:2a02:6b8:0:1a2d::27]) by forward5j.cmail.yandex.net (Yandex) with ESMTP id 0DC6F21190 for ; Wed, 12 Jul 2017 16:00:15 +0300 (MSK) Received: from smtp3o.mail.yandex.net (localhost.localdomain [127.0.0.1]) by smtp3o.mail.yandex.net (Yandex) with ESMTP id 5DCCB2940CDB for ; Wed, 12 Jul 2017 16:00:12 +0300 (MSK) Received: by smtp3o.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id 1plU0zQJQm-0CvOHQBJ; Wed, 12 Jul 2017 16:00:12 +0300 (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (Client certificate not present) X-Yandex-Suid-Status: 1 0 From: Github ODP bot To: lng-odp@lists.linaro.org Date: Wed, 12 Jul 2017 16:00:04 +0300 Message-Id: <1499864406-10454-2-git-send-email-odpbot@yandex.ru> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1499864406-10454-1-git-send-email-odpbot@yandex.ru> References: <1499864406-10454-1-git-send-email-odpbot@yandex.ru> Github-pr-num: 73 Subject: [lng-odp] [PATCH v2 1/3] example: ipfragaddress: fix compilation with clang X-BeenThere: lng-odp@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "The OpenDataPlane \(ODP\) List" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: lng-odp-bounces@lists.linaro.org Sender: "lng-odp" From: Dmitry Eremin-Solenikov Clang 3.8 is stricter than GCC wrt register allocation vs 128-bit variables. Sometimes it can not understand using 128-bit var in place of 64-bit register resulting in the following errors: /odp_ipfragreass_atomics_arm.h:18:51: error: value size does not match register size specified by the constraint and modifier [-Werror,-Wasm-operand-widths] __asm__ volatile("ldaxp %0, %H0, [%1]" : "=&r" (old) ^ ./odp_ipfragreass_atomics_arm.h:18:27: note: use constraint modifier "w" __asm__ volatile("ldaxp %0, %H0, [%1]" : "=&r" (old) Explicitly pass low and high parts of 128-bit variable in separate assembly parameters. Signed-off-by: Dmitry Eremin-Solenikov --- /** Email created from pull request 73 (lumag:cross-2) ** https://github.com/Linaro/odp/pull/73 ** Patch: https://github.com/Linaro/odp/pull/73.patch ** Base sha: 7fc6d27e937b57b31360b07028388c811f8300dc ** Merge commit sha: 3dd283d7e61ba21beed2607ef200584754f22d76 **/ example/ipfragreass/odp_ipfragreass_atomics_arm.h | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/example/ipfragreass/odp_ipfragreass_atomics_arm.h b/example/ipfragreass/odp_ipfragreass_atomics_arm.h index 99c37a77..94ccd00e 100644 --- a/example/ipfragreass/odp_ipfragreass_atomics_arm.h +++ b/example/ipfragreass/odp_ipfragreass_atomics_arm.h @@ -13,26 +13,33 @@ static inline __int128 lld(__int128 *var, int mo) { __int128 old; + uint64_t lo, hi; if (mo == __ATOMIC_ACQUIRE) - __asm__ volatile("ldaxp %0, %H0, [%1]" : "=&r" (old) + __asm__ volatile("ldaxp %0, %1, [%2]" : "=r" (lo), "=r" (hi) : "r" (var) : "memory"); else /* mo == __ATOMIC_RELAXED */ - __asm__ volatile("ldxp %0, %H0, [%1]" : "=&r" (old) + __asm__ volatile("ldxp %0, %1, [%2]" : "=r" (lo), "=r" (hi) : "r" (var) : ); + old = hi; + old <<= 64; + old |= lo; + return old; + } static inline uint32_t scd(__int128 *var, __int128 neu, int mo) { uint32_t ret; + uint64_t lo = neu, hi = neu >> 64; if (mo == __ATOMIC_RELEASE) - __asm__ volatile("stlxp %w0, %1, %H1, [%2]" : "=&r" (ret) - : "r" (neu), "r" (var) : "memory"); + __asm__ volatile("stlxp %w0, %1, %2, [%3]" : "=&r" (ret) + : "r" (lo), "r" (hi), "r" (var) : "memory"); else /* mo == __ATOMIC_RELAXED */ - __asm__ volatile("stxp %w0, %1, %H1, [%2]" : "=&r" (ret) - : "r" (neu), "r" (var) : ); + __asm__ volatile("stxp %w0, %1, %2, [%3]" : "=&r" (ret) + : "r" (lo), "r" (hi), "r" (var) : "memory"); return ret; }