From patchwork Sat Apr 1 07:25:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 96538 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1058149qgd; Sat, 1 Apr 2017 00:26:51 -0700 (PDT) X-Received: by 10.99.155.17 with SMTP id r17mr6663959pgd.193.1491031611200; Sat, 01 Apr 2017 00:26:51 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 2si7403635plb.41.2017.04.01.00.26.51; Sat, 01 Apr 2017 00:26:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751267AbdDAH0t (ORCPT + 6 others); Sat, 1 Apr 2017 03:26:49 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:5294 "EHLO dggrg01-dlp.huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1750793AbdDAH0q (ORCPT ); Sat, 1 Apr 2017 03:26:46 -0400 Received: from 172.30.72.53 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.53]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ALV84944; Sat, 01 Apr 2017 15:26:11 +0800 (CST) Received: from localhost (10.177.23.32) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Sat, 1 Apr 2017 15:26:00 +0800 From: Ding Tianhong To: , , , , , , , , CC: Ding Tianhong Subject: [PATCH net-next 1/4] ixgbe: sparc: rename the ARCH_WANT_RELAX_ORDER to IXGBE_ALLOW_RELAXED_ORDER Date: Sat, 1 Apr 2017 15:25:51 +0800 Message-ID: <1491031554-19516-2-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1491031554-19516-1-git-send-email-dingtianhong@huawei.com> References: <1491031554-19516-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.58DF5614.002E, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: f0a0384365ed7cbd438a1a63a3f74b6e Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Till now only the Intel ixgbe could support enable Relaxed ordering in the drivers for special architecture, but the ARCH_WANT_RELAX_ORDER is looks like a general name for all arch, so rename to a specific name for intel card looks more appropriate. Signed-off-by: Ding Tianhong --- arch/Kconfig | 2 +- arch/sparc/Kconfig | 2 +- drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) -- 1.9.0 diff --git a/arch/Kconfig b/arch/Kconfig index cd211a1..bc0ab44 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -844,7 +844,7 @@ config STRICT_MODULE_RWX and non-text memory will be made non-executable. This provides protection against certain security exploits (e.g. writing to text) -config ARCH_WANT_RELAX_ORDER +config IXGBE_ALLOW_RELAXED_ORDER bool source "kernel/gcov/Kconfig" diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index 68ac5c7..f56bcf4 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -44,7 +44,7 @@ config SPARC select CPU_NO_EFFICIENT_FFS select HAVE_ARCH_HARDENED_USERCOPY select PROVE_LOCKING_SMALL if PROVE_LOCKING - select ARCH_WANT_RELAX_ORDER + select IXGBE_ALLOW_RELAXED_ORDER config SPARC32 def_bool !64BIT diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c index c38d50c..563ea15 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c @@ -350,7 +350,7 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) } IXGBE_WRITE_FLUSH(hw); -#ifndef CONFIG_ARCH_WANT_RELAX_ORDER +#ifndef CONFIG_IXGBE_ALLOW_RELAX_ORDER /* Disable relaxed ordering */ for (i = 0; i < hw->mac.max_tx_queues; i++) { u32 regval;