From patchwork Sun Jan 10 15:30:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Chulski X-Patchwork-Id: 360879 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EE5BC433DB for ; Sun, 10 Jan 2021 15:34:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 421AC2333E for ; Sun, 10 Jan 2021 15:34:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727076AbhAJPeS (ORCPT ); Sun, 10 Jan 2021 10:34:18 -0500 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:31420 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727035AbhAJPeR (ORCPT ); Sun, 10 Jan 2021 10:34:17 -0500 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 10AFQ7gE023449; Sun, 10 Jan 2021 07:31:29 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=G1b2l3iVNOoN96kgKwJR3Ya1I4AU0P+tvorIEIjPxWE=; b=asyxuSrv3tbsDm6aN3T2/ZaCTPk+ZWKhfS2ZZBqjQTqvrrohkqeZMN15IR6oLRfoEvV+ yO51Z4vEZPd5cqgjXQHcezVyRvI6JckPYvkvK/2BnSqkVenPYM/4vKE7qjKMTdml/Prb Fbiuc5kbThNGf5KZ9KBddHmxp/OzMURp1CW1kc5rrppgZwBJDyg+dugdMJHU8i2WEk3W 71TlDtkpUwpp64OAHdl5zV1HSbbAHhheZx2WkCyIM8ngGhqgKZ496s8TQynZIuTNH94z ZcS4jFYWh3xOQ2lhjuXEnZ4fzcZG10YJiU+oakmtCAL1VXgr8RCljUdeLVh7gg4X723m 4g== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 35ycvphvdr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 10 Jan 2021 07:31:29 -0800 Received: from SC-EXCH03.marvell.com (10.93.176.83) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 10 Jan 2021 07:31:27 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 10 Jan 2021 07:31:27 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 10 Jan 2021 07:31:27 -0800 Received: from stefan-pc.marvell.com (stefan-pc.marvell.com [10.5.25.21]) by maili.marvell.com (Postfix) with ESMTP id 2BAB03F703F; Sun, 10 Jan 2021 07:31:23 -0800 (PST) From: To: CC: , , , , , , , , , , , Subject: [PATCH RFC net-next 09/19] net: mvpp2: add FCA RXQ non occupied descriptor threshold Date: Sun, 10 Jan 2021 17:30:13 +0200 Message-ID: <1610292623-15564-10-git-send-email-stefanc@marvell.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1610292623-15564-1-git-send-email-stefanc@marvell.com> References: <1610292623-15564-1-git-send-email-stefanc@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2021-01-09_13:2021-01-07,2021-01-09 signatures=0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Stefan Chulski RXQ non occupied descriptor threshold would be used by Flow Control Firmware feature to move to the XOFF mode. RXQ non occupied threshold would change interrupt cause that polled by CM3 Firmware. Actual non occupied interrupt masked and won't trigger interrupt. Signed-off-by: Stefan Chulski --- drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 3 ++ drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 29 ++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h index 0861c0b..3df8f60 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h @@ -295,6 +295,8 @@ #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31) #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0 +#define MVPP2_ISR_RX_ERR_CAUSE_REG(port) (0x5520 + 4 * (port)) +#define MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK 0x00ff /* Buffer Manager registers */ #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4)) @@ -764,6 +766,7 @@ #define MSS_SRAM_SIZE 0x800 #define FC_QUANTA 0xFFFF #define FC_CLK_DIVIDER 0x140 +#define MSS_THRESHOLD_STOP 768 /* RX buffer constants */ #define MVPP2_SKB_SHINFO_SIZE \ diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c index b5b7902..4d4e886 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c @@ -1154,6 +1154,9 @@ static void mvpp2_interrupts_mask(void *arg) mvpp2_thread_write(port->priv, mvpp2_cpu_to_thread(port->priv, smp_processor_id()), MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); + mvpp2_thread_write(port->priv, + mvpp2_cpu_to_thread(port->priv, smp_processor_id()), + MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0); } /* Unmask the current thread's Rx/Tx interrupts. @@ -1177,6 +1180,10 @@ static void mvpp2_interrupts_unmask(void *arg) mvpp2_thread_write(port->priv, mvpp2_cpu_to_thread(port->priv, smp_processor_id()), MVPP2_ISR_RX_TX_MASK_REG(port->id), val); + mvpp2_thread_write(port->priv, + mvpp2_cpu_to_thread(port->priv, smp_processor_id()), + MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), + MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK); } static void @@ -1201,6 +1208,9 @@ static void mvpp2_interrupts_unmask(void *arg) mvpp2_thread_write(port->priv, v->sw_thread_id, MVPP2_ISR_RX_TX_MASK_REG(port->id), val); + mvpp2_thread_write(port->priv, v->sw_thread_id, + MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), + MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK); } } @@ -2406,6 +2416,22 @@ static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) } } +/* Routine set the number of non-occupied descriptors threshold that change + * interrupt error cause polled by FW Flow Control + */ +void mvpp2_set_rxq_free_tresh(struct mvpp2_port *port, + struct mvpp2_rx_queue *rxq) +{ + u32 val; + + mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); + + val = mvpp2_read(port->priv, MVPP2_RXQ_THRESH_REG); + val &= ~MVPP2_RXQ_NON_OCCUPIED_MASK; + val |= MSS_THRESHOLD_STOP << MVPP2_RXQ_NON_OCCUPIED_OFFSET; + mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val); +} + /* Set the number of packets that will be received before Rx interrupt * will be generated by HW. */ @@ -2661,6 +2687,9 @@ static int mvpp2_rxq_init(struct mvpp2_port *port, mvpp2_rx_pkts_coal_set(port, rxq); mvpp2_rx_time_coal_set(port, rxq); + /* Set the number of non occupied descriptors threshold */ + mvpp2_set_rxq_free_tresh(port, rxq); + /* Add number of descriptors ready for receiving packets */ mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);