| Message ID | 1610292623-15564-7-git-send-email-stefanc@marvell.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | net: mvpp2: Add TX Flow Control support | expand |
On Sun, Jan 10, 2021 at 05:30:10PM +0200, stefanc@marvell.com wrote: > From: Stefan Chulski <stefanc@marvell.com> > > BM pool size increased to support Firmware Flow Control. > Minimum depletion thresholds to support FC is 1024 buffers. > BM pool size increased to 2048 to have some 1024 buffers > space between depletion thresholds and BM pool size. > > Signed-off-by: Stefan Chulski <stefanc@marvell.com> > --- > drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > index 89b3ede..8dc669d 100644 > --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > @@ -851,8 +851,8 @@ enum mvpp22_ptp_packet_format { > #define MVPP22_PTP_TIMESTAMPQUEUESELECT BIT(18) > > /* BM constants */ > -#define MVPP2_BM_JUMBO_BUF_NUM 512 > -#define MVPP2_BM_LONG_BUF_NUM 1024 > +#define MVPP2_BM_JUMBO_BUF_NUM 2048 > +#define MVPP2_BM_LONG_BUF_NUM 2048 Hi Stefan Jumbo used to be 1/2 of regular. Do you know why? It would be nice to have a comment in the commit message about why it is O.K. to change the ratio of jumbo to regular frames, and what if anything this does for memory requirements. Andrew
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h index 89b3ede..8dc669d 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h @@ -851,8 +851,8 @@ enum mvpp22_ptp_packet_format { #define MVPP22_PTP_TIMESTAMPQUEUESELECT BIT(18) /* BM constants */ -#define MVPP2_BM_JUMBO_BUF_NUM 512 -#define MVPP2_BM_LONG_BUF_NUM 1024 +#define MVPP2_BM_JUMBO_BUF_NUM 2048 +#define MVPP2_BM_LONG_BUF_NUM 2048 #define MVPP2_BM_SHORT_BUF_NUM 2048 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4) #define MVPP2_BM_POOL_PTR_ALIGN 128