From patchwork Mon Feb 8 08:32:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Chulski X-Patchwork-Id: 379974 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B68D1C4332D for ; Mon, 8 Feb 2021 08:38:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 82AF364E45 for ; Mon, 8 Feb 2021 08:38:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230495AbhBHIiS (ORCPT ); Mon, 8 Feb 2021 03:38:18 -0500 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:6020 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S230299AbhBHIf3 (ORCPT ); Mon, 8 Feb 2021 03:35:29 -0500 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1188Tp4Z021072; Mon, 8 Feb 2021 00:34:38 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=UrL4S17emqCRulz9TWUJtPhwJxRUYZLo7+JL/qJJ06c=; b=XEUpplIEQWY65J+Td0pjT/kFI58HPYY/A3dCPxR5ptLVb6Jsso+2Fr2M7ohjJAl/tLiA g5vDs4z0PM+4RszuQ+Ae+9FOR894QX+62P6F0FbDp5PMnrjWdfCatRDMmPJ6ZQ6vY/g4 hMp6b9TSx7haRFabIiPXeo67A/qOqDv72Af2hmaDSIdIgKg+qUIz/4wwUOdVm2meU1G4 wVDBnHpWsw+oUp6a23ys3pzQmOX03MLAjMBxvlc7+zNdGGMoRaTxtf0ZmZk+LjHS+1+U uDO+Fzvo7st2lGLm1SGqzMLOgXoRDafPyjnFOresIiKzNByp+ZABAcK+Aau5beXR8yKl hA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 36hsbrc54j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 08 Feb 2021 00:34:38 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 8 Feb 2021 00:34:36 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 8 Feb 2021 00:34:36 -0800 Received: from stefan-pc.marvell.com (stefan-pc.marvell.com [10.5.25.21]) by maili.marvell.com (Postfix) with ESMTP id BDAFD3F7040; Mon, 8 Feb 2021 00:34:32 -0800 (PST) From: To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH v10 net-next 09/15] net: mvpp2: enable global flow control Date: Mon, 8 Feb 2021 10:32:41 +0200 Message-ID: <1612773167-22490-10-git-send-email-stefanc@marvell.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1612773167-22490-1-git-send-email-stefanc@marvell.com> References: <1612773167-22490-1-git-send-email-stefanc@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.737 definitions=2021-02-08_02:2021-02-05,2021-02-08 signatures=0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Stefan Chulski This patch enables global flow control in FW and in the phylink validate mask. Signed-off-by: Stefan Chulski --- drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 11 +++++-- drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 30 +++++++++++++++++++- 2 files changed, 37 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h index d2cc513c..8945fb9 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h @@ -763,9 +763,11 @@ ((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) /* MSS Flow control */ -#define FC_QUANTA 0xFFFF -#define FC_CLK_DIVIDER 100 -#define MSS_THRESHOLD_STOP 768 +#define MSS_FC_COM_REG 0 +#define FLOW_CONTROL_ENABLE_BIT BIT(0) +#define FC_QUANTA 0xFFFF +#define FC_CLK_DIVIDER 100 +#define MSS_THRESHOLD_STOP 768 /* RX buffer constants */ #define MVPP2_SKB_SHINFO_SIZE \ @@ -1017,6 +1019,9 @@ struct mvpp2 { /* page_pool allocator */ struct page_pool *page_pool[MVPP2_PORT_MAX_RXQ]; + + /* Global TX Flow Control config */ + bool global_tx_fc; }; struct mvpp2_pcpu_stats { diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c index 8b4073c..027101b 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c @@ -91,6 +91,16 @@ static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu) return cpu % priv->nthreads; } +static void mvpp2_cm3_write(struct mvpp2 *priv, u32 offset, u32 data) +{ + writel(data, priv->cm3_base + offset); +} + +static u32 mvpp2_cm3_read(struct mvpp2 *priv, u32 offset) +{ + return readl(priv->cm3_base + offset); +} + static struct page_pool * mvpp2_create_page_pool(struct device *dev, int num, int len, enum dma_data_direction dma_dir) @@ -5950,6 +5960,11 @@ static void mvpp2_phylink_validate(struct phylink_config *config, phylink_set(mask, Autoneg); phylink_set_port_modes(mask); + if (port->priv->global_tx_fc) { + phylink_set(mask, Pause); + phylink_set(mask, Asym_Pause); + } + switch (state->interface) { case PHY_INTERFACE_MODE_10GBASER: case PHY_INTERFACE_MODE_XAUI: @@ -6951,7 +6966,7 @@ static int mvpp2_probe(struct platform_device *pdev) struct resource *res; void __iomem *base; int i, shared; - int err; + int err, val; priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -7003,6 +7018,10 @@ static int mvpp2_probe(struct platform_device *pdev) err = mvpp2_get_sram(pdev, priv); if (err) dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n"); + + /* Enable global Flow Control only if handler to SRAM not NULL */ + if (priv->cm3_base) + priv->global_tx_fc = true; } if (priv->hw_version != MVPP21 && dev_of_node(&pdev->dev)) { @@ -7168,6 +7187,15 @@ static int mvpp2_probe(struct platform_device *pdev) goto err_port_probe; } + /* Enable global flow control. In this stage global + * flow control enabled, but still disabled per port. + */ + if (priv->global_tx_fc && priv->hw_version != MVPP21) { + val = mvpp2_cm3_read(priv, MSS_FC_COM_REG); + val |= FLOW_CONTROL_ENABLE_BIT; + mvpp2_cm3_write(priv, MSS_FC_COM_REG, val); + } + mvpp2_dbgfs_init(priv, pdev->name); platform_set_drvdata(pdev, priv);