From patchwork Tue Apr 6 22:11:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 417288 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FF68C433B4 for ; Tue, 6 Apr 2021 22:12:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3E270613CF for ; Tue, 6 Apr 2021 22:12:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242614AbhDFWMa (ORCPT ); Tue, 6 Apr 2021 18:12:30 -0400 Received: from mail.kernel.org ([198.145.29.99]:52696 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344072AbhDFWMN (ORCPT ); Tue, 6 Apr 2021 18:12:13 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id CCE99613D0; Tue, 6 Apr 2021 22:12:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1617747125; bh=T5IlwtM8m9MQJwSEjJ13nFxx/s9cm5Py688W2zMXx5g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kKnbj1ZTIi3JCxORPoyG3w+rMd0Md9crk1ooVSkPB9djjO4JPoa4scl/TMxKOCfZ7 gLEOYI9MadVbnILXaLqAQKbXzHmCyt1ncJn5Uhws2sg9Fjr1jj6zexZrmNp2rN2mUj /z2uVxOGHwlZo3E3e62auC33N23bw6QHYD70IIJgpu1+EGjTFB1EvM+LcdzpbqYn1y 23oIjfOBqje0JF+GFNqT45+52N+1GgSK3aJBC8qOUt671Nw4JRYAmrbAVX9DlCuI3k /qi5It1z3uUXImrx0+1mYPzy2Yl4Nd5ga299LLNUpx67ioXB3eMdOkqLPMm4TR52EW E6YZolgadt6aQ== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: netdev@vger.kernel.org, Russell King Cc: "David S . Miller" , Florian Fainelli , Heiner Kallweit , kuba@kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH net-next v3 12/18] net: phy: marvell10g: support other MACTYPEs Date: Wed, 7 Apr 2021 00:11:01 +0200 Message-Id: <20210406221107.1004-13-kabel@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210406221107.1004-1-kabel@kernel.org> References: <20210406221107.1004-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Currently the only "changing" MACTYPE we support is when the PHY changes between 10gbase-r / 5gbase-r / 2500base-x / sgmii Add support for usxgmii xaui / 5gbase-r / 2500base-x / sgmii rxaui / 5gbase-r / 2500base-x / sgmii and also 5gbase-r / 2500base-x / sgmii for 88E2110. Signed-off-by: Marek Behún --- drivers/net/phy/marvell10g.c | 90 +++++++++++++++++++++--------------- 1 file changed, 54 insertions(+), 36 deletions(-) diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index a7c7c87201fa..2fd823318de8 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -508,10 +508,18 @@ static int mv2110_init_interface(struct phy_device *phydev, int mactype) priv->rate_match = false; - if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) { + if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) priv->rate_match = true; + + if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII) + priv->const_interface = PHY_INTERFACE_MODE_USXGMII; + else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) priv->const_interface = PHY_INTERFACE_MODE_10GBASER; - } + else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER || + mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN) + priv->const_interface = PHY_INTERFACE_MODE_NA; + else + return -EINVAL; return 0; } @@ -527,12 +535,20 @@ static int mv3310_init_interface(struct phy_device *phydev, int mactype) mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH) priv->rate_match = true; - if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) + if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII) + priv->const_interface = PHY_INTERFACE_MODE_USXGMII; + else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH || + mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN || + mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER) priv->const_interface = PHY_INTERFACE_MODE_10GBASER; - else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH) + else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH || + mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI) priv->const_interface = PHY_INTERFACE_MODE_RXAUI; - else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH) + else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH || + mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI) priv->const_interface = PHY_INTERFACE_MODE_XAUI; + else + return -EINVAL; return 0; } @@ -558,8 +574,10 @@ static int mv3310_config_init(struct phy_device *phydev) return mactype; err = chip->init_interface(phydev, mactype); - if (err) + if (err) { + phydev_err(phydev, "MACTYPE configuration invalid\n"); return err; + } /* Enable EDPD mode - saving 600mW */ return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS); @@ -669,44 +687,44 @@ static void mv3310_update_interface(struct phy_device *phydev) { struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); + if (!phydev->link) + return; + /* In all of the "* with Rate Matching" modes the PHY interface is fixed * at 10Gb. The PHY adapts the rate to actual wire speed with help of * internal 16KB buffer. + * + * In USXGMII mode the PHY interface mode is also fixed. */ - if (priv->rate_match) { + if (priv->rate_match || + priv->const_interface == PHY_INTERFACE_MODE_USXGMII) { phydev->interface = priv->const_interface; return; } - if ((phydev->interface == PHY_INTERFACE_MODE_SGMII || - phydev->interface == PHY_INTERFACE_MODE_2500BASEX || - phydev->interface == PHY_INTERFACE_MODE_5GBASER || - phydev->interface == PHY_INTERFACE_MODE_10GBASER) && - phydev->link) { - /* The PHY automatically switches its serdes interface (and - * active PHYXS instance) between Cisco SGMII, 10GBase-R and - * 2500BaseX modes according to the speed. Florian suggests - * setting phydev->interface to communicate this to the MAC. - * Only do this if we are already in one of the above modes. - */ - switch (phydev->speed) { - case SPEED_10000: - phydev->interface = PHY_INTERFACE_MODE_10GBASER; - break; - case SPEED_5000: - phydev->interface = PHY_INTERFACE_MODE_5GBASER; - break; - case SPEED_2500: - phydev->interface = PHY_INTERFACE_MODE_2500BASEX; - break; - case SPEED_1000: - case SPEED_100: - case SPEED_10: - phydev->interface = PHY_INTERFACE_MODE_SGMII; - break; - default: - break; - } + /* The PHY automatically switches its serdes interface (and active PHYXS + * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R / + * xaui / rxaui modes according to the speed. + * Florian suggests setting phydev->interface to communicate this to the + * MAC. Only do this if we are already in one of the above modes. + */ + switch (phydev->speed) { + case SPEED_10000: + phydev->interface = priv->const_interface; + break; + case SPEED_5000: + phydev->interface = PHY_INTERFACE_MODE_5GBASER; + break; + case SPEED_2500: + phydev->interface = PHY_INTERFACE_MODE_2500BASEX; + break; + case SPEED_1000: + case SPEED_100: + case SPEED_10: + phydev->interface = PHY_INTERFACE_MODE_SGMII; + break; + default: + break; } }