From patchwork Fri Mar 9 16:35:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 131156 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp1194893lja; Fri, 9 Mar 2018 08:37:41 -0800 (PST) X-Google-Smtp-Source: AG47ELudLcKGo5mUqF/BbjBU2G/TGvpr1yBdE0hjH97NzWMtvNTzSZBN08KJXa4HAwneuTnE148f X-Received: by 2002:a24:108c:: with SMTP id 134-v6mr4096935ity.94.1520613461790; Fri, 09 Mar 2018 08:37:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520613461; cv=none; d=google.com; s=arc-20160816; b=GQvIHaOjLCfCqDcI0j7QU7U4dJW+O02FOv/UyEpQXpVoK1Z0vVjoJFjZoH1sRz2vuR bjrrrpiq9W/teMwZSaRNvd+A1DsvXFyFTQHveYw81hwFjxIFkDDIuMEtAhRFlw9qDtau WAr03oD+sI6eIi+PHOoddYKT6xitZYK5LAECu61WOsdP6GI7/MWaOVIj2s/jAe1CKzHL fnxryPgQkGxKR2vGQHMKKaMxArPeSYfQkpvR8PrekOu6q8awJxDA5/QZ+HrBY3i7HbUX p/tCzuWgEFOI/Qe4+mU7f3ZQ/mVPOgbkgO92jZ3dxoI0X+qk8LoerCHotvqce1c3aEe5 ONBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=2MU1sY5c/t1IMby3fF6Zrqy8KBzU1drIUVOxuuqMOdk=; b=u/ww6RzHA8v+EjX6QSK9i8mnH0BOlhu/B+RlGbnr3GWVrFYnQO8HAZPEzWxWUgweb/ GwfGk+6Ws2J/e1czwC7qRXFC8wuXsV0x8wVseKAtnKYFGNrt3gyPzKhu4hLUTpXqm0Nl kux9TK0RinhnrPsfBvi+JLWNol3JaXXGrYZOo6xCGOhrMuWVwIIaI7/2DXTOEC19urd5 rABppIZm4JLGY6jcAR7b6DUGefz8bS2WVwJiYx5KVPjdH9W/1LRkbsxWgGaFNlKrIkTk wWHuSPp3H/X9o+XUtY3r+tetEPfKPM8liVJqLwPz03ikXSUdenz2tazke1w98pF+CZYO aypA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id l93si1205079iod.321.2018.03.09.08.37.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Mar 2018 08:37:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euKzQ-0000hP-Py; Fri, 09 Mar 2018 16:35:28 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euKzP-0000gC-ND for xen-devel@lists.xenproject.org; Fri, 09 Mar 2018 16:35:27 +0000 X-Inumbo-ID: 33b5021c-23b8-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 33b5021c-23b8-11e8-b9b1-635ca7ef6cff; Fri, 09 Mar 2018 16:37:48 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7CA171529; Fri, 9 Mar 2018 08:35:20 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9183B3F487; Fri, 9 Mar 2018 08:35:19 -0800 (PST) From: julien.grall@arm.com To: xen-devel@lists.xenproject.org Date: Fri, 9 Mar 2018 16:35:07 +0000 Message-Id: <20180309163511.18808-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180309163511.18808-1-julien.grall@arm.com> References: <20180309163511.18808-1-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 2/6] xen/arm: vgic: Override the group in lr everytime X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Julien Grall At the moment, write_lr is assuming the caller will set correctly the group. However the group should always be 0 when the guest is using vGICv2 and 1 for vGICv3. As the caller should not care about the group, override it directly. With that change, write_lr is now behaving like update_lr for the group. Signed-off-by: Julien Grall --- xen/arch/arm/gic-v2.c | 4 +--- xen/arch/arm/gic-v3.c | 11 ++++++++--- xen/include/asm-arm/gic.h | 1 - 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index f16e17c1a3..fc105c08b8 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -469,7 +469,6 @@ static void gicv2_read_lr(int lr, struct gic_lr *lr_reg) lr_reg->priority = (lrv >> GICH_V2_LR_PRIORITY_SHIFT) & GICH_V2_LR_PRIORITY_MASK; lr_reg->state = (lrv >> GICH_V2_LR_STATE_SHIFT) & GICH_V2_LR_STATE_MASK; lr_reg->hw_status = (lrv >> GICH_V2_LR_HW_SHIFT) & GICH_V2_LR_HW_MASK; - lr_reg->grp = (lrv >> GICH_V2_LR_GRP_SHIFT) & GICH_V2_LR_GRP_MASK; } static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) @@ -483,8 +482,7 @@ static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) ((uint32_t)(lr_reg->state & GICH_V2_LR_STATE_MASK) << GICH_V2_LR_STATE_SHIFT) | ((uint32_t)(lr_reg->hw_status & GICH_V2_LR_HW_MASK) - << GICH_V2_LR_HW_SHIFT) | - ((uint32_t)(lr_reg->grp & GICH_V2_LR_GRP_MASK) << GICH_V2_LR_GRP_SHIFT) ); + << GICH_V2_LR_HW_SHIFT)); writel_gich(lrv, GICH_LR + lr * 4); } diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 09b49a07d5..0dfa1a1e08 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1012,7 +1012,6 @@ static void gicv3_read_lr(int lr, struct gic_lr *lr_reg) lr_reg->priority = (lrv >> ICH_LR_PRIORITY_SHIFT) & ICH_LR_PRIORITY_MASK; lr_reg->state = (lrv >> ICH_LR_STATE_SHIFT) & ICH_LR_STATE_MASK; lr_reg->hw_status = (lrv >> ICH_LR_HW_SHIFT) & ICH_LR_HW_MASK; - lr_reg->grp = (lrv >> ICH_LR_GRP_SHIFT) & ICH_LR_GRP_MASK; } static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) @@ -1023,8 +1022,14 @@ static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) ((u64)(lr->virq & ICH_LR_VIRTUAL_MASK) << ICH_LR_VIRTUAL_SHIFT) | ((u64)(lr->priority & ICH_LR_PRIORITY_MASK) << ICH_LR_PRIORITY_SHIFT)| ((u64)(lr->state & ICH_LR_STATE_MASK) << ICH_LR_STATE_SHIFT) | - ((u64)(lr->hw_status & ICH_LR_HW_MASK) << ICH_LR_HW_SHIFT) | - ((u64)(lr->grp & ICH_LR_GRP_MASK) << ICH_LR_GRP_SHIFT) ); + ((u64)(lr->hw_status & ICH_LR_HW_MASK) << ICH_LR_HW_SHIFT) ); + + /* + * When the guest is using vGICv3, all the IRQs are Group 1. Group 0 + * would result in a FIQ, which will not be expected by the guest OS. + */ + if ( current->domain->arch.vgic.version == GIC_V3 ) + lrv |= ICH_LR_GRP1; gicv3_ich_write_lr(lr_reg, lrv); } diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 49cb94f792..1eb08b856e 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -211,7 +211,6 @@ struct gic_lr { uint8_t priority; uint8_t state; uint8_t hw_status; - uint8_t grp; }; enum gic_version {