From patchwork Tue Jul 23 21:35:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 169568 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp9377150ilk; Tue, 23 Jul 2019 14:37:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqwqYOtOSXVKd0x4V9dzJWbW5WKM9oqUojP1rF6XbZfCCKeFKWXlbFvSQ0g0L6A5c8M36rMT X-Received: by 2002:a05:6638:5:: with SMTP id z5mr9252773jao.58.1563917862454; Tue, 23 Jul 2019 14:37:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1563917862; cv=none; d=google.com; s=arc-20160816; b=Jes48W0W74w2B3YCqh3I+D6meLdw1+2U4yQiTM0p2dnBdCASEAdWgxb1jwXmf+bLwF SyxQAqGkLN7DdWL1HFNKNZ1+N9x/YpSvPuFCcDFFS/JOS1F1oLfeJRQiHaDnrY/12APQ g6FS+GGWIzcD2kNCfVtmW1E1b1OUgCwGCi1miHnQ5Xyki8f0EZhBlbp5cXAtdSQCLHSS WG9egw8QzKLFfwbMyF1OAfSorKirmJti2czB8fGm4nvnL2Sm2H2/fJIGMuqLjXR6yUWF TMkAdcumQ1yiZ3CNbyERieEMx33j9BFqzvjCWEWeiqUl+t+v/kn+nFZdNwfZZPc9uKEl RFxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=tBCw0P7Z40dCQRtCjpGo/jIaWN3mMkjRgJtlRJJ1zvw=; b=rTBKux52QjfdWIbt/utQW6B8hmxVaqBCS4zidR/z8rgg+g6xrKaFNwsU8p1xFNXrZb /J3GSHK0bWG4kDbYd16zfy+IRkAy1r5CzMSO71o+ZDhndu02LLNt0w7vyIhdXcTQ7Wls sllc3yaKkSJmefhnCzqCyxVhgVd2CrRBOVzirFJnZGFkKPf7/MC1y/LfUZj5AvdJTGD+ oNl+HiJ7tMO99KWE68eKNqZxJBENGdUcA1Ufyl2VbJpjsY9u9kCY2vjXpSU1OfYLqTvP wIgVO2tdzU6cDKJoHqPYxbE0bcaEgqjwQnXmJcqBQ4/amLbeFZvJIM25+muRLAEwnLPW AEcA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 187si4069992jaz.24.2019.07.23.14.37.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Jul 2019 14:37:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hq2S7-0001wH-AI; Tue, 23 Jul 2019 21:36:07 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hq2S5-0001vW-69 for xen-devel@lists.xenproject.org; Tue, 23 Jul 2019 21:36:05 +0000 X-Inumbo-ID: de4fdb74-ad91-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id de4fdb74-ad91-11e9-8980-bc764e045a96; Tue, 23 Jul 2019 21:36:02 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0D0341596; Tue, 23 Jul 2019 14:36:02 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 09A133F71F; Tue, 23 Jul 2019 14:36:00 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 23 Jul 2019 22:35:48 +0100 Message-Id: <20190723213553.22300-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190723213553.22300-1-julien.grall@arm.com> References: <20190723213553.22300-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 2/7] xen/arm: SCTLR_EL1 is a 64-bit register on Arm64 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Wei Liu , George Dunlap , Ian Jackson , Julien Grall , Volodymyr Babchuk MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" On Arm64, system registers are always 64-bit including SCTLR_EL1. However, Xen is assuming this is 32-bit because earlier revision of Armv8 had the top 32-bit RES0 (see ARM DDI0595.b). >From Armv8.5, some bits in [63:32] will be defined and allowed to be modified by the guest. So we would effectively reset those bits to 0 after each context switch. This means the guest may not function correctly afterwards. Rather than resetting to 0 the bits [63:32], preserve them acxcross context switch. Note that the corresponding register on Arm32 (i.e SCTLR) is always 32-bit. So we need to use register_t anywhere we deal the SCTLR{,_EL1}. Outside interface is switched to use 64-bit to allow ABI compatibility between 32-bit and 64-bit. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini --- All the other system registers should be switched to 64-bit. This is done separatly as this is the only system register that currently not save/restore correctly. I would consider to backport it as we would end up to disable features behind the back of the guest. --- tools/xentrace/xenctx.c | 4 +++- xen/arch/arm/guest_walk.c | 2 +- xen/arch/arm/traps.c | 10 +++++----- xen/include/asm-arm/domain.h | 3 ++- xen/include/asm-arm/p2m.h | 4 ++-- xen/include/public/arch-arm.h | 4 ++-- 6 files changed, 15 insertions(+), 12 deletions(-) diff --git a/tools/xentrace/xenctx.c b/tools/xentrace/xenctx.c index e647179e19..2fa864f867 100644 --- a/tools/xentrace/xenctx.c +++ b/tools/xentrace/xenctx.c @@ -598,6 +598,8 @@ static void print_ctx_32(vcpu_guest_context_t *ctx) printf("r12_fiq: %08"PRIx32"\n", regs->r12_fiq); printf("\n"); + /* SCTLR is always 32-bit */ + printf("SCTLR: %08"PRIx32"\n", (uint32_t)ctx->sctlr); } #ifdef __aarch64__ @@ -659,6 +661,7 @@ static void print_ctx_64(vcpu_guest_context_t *ctx) printf("x28: %016"PRIx64"\t", regs->x28); printf("x29: %016"PRIx64"\n", regs->x29); printf("\n"); + printf("SCTLR_EL1: %016"PRIx64"\n", ctx->sctlr); } #endif /* __aarch64__ */ @@ -675,7 +678,6 @@ static void print_ctx(vcpu_guest_context_any_t *ctx_any) print_ctx_32(ctx); #endif - printf("SCTLR: %08"PRIx32"\n", ctx->sctlr); printf("TTBCR: %016"PRIx64"\n", ctx->ttbcr); printf("TTBR0: %016"PRIx64"\n", ctx->ttbr0); printf("TTBR1: %016"PRIx64"\n", ctx->ttbr1); diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c index c6d6e23bf5..a1cdd7f4af 100644 --- a/xen/arch/arm/guest_walk.c +++ b/xen/arch/arm/guest_walk.c @@ -589,7 +589,7 @@ static bool guest_walk_ld(const struct vcpu *v, bool guest_walk_tables(const struct vcpu *v, vaddr_t gva, paddr_t *ipa, unsigned int *perms) { - uint32_t sctlr = READ_SYSREG(SCTLR_EL1); + register_t sctlr = READ_SYSREG(SCTLR_EL1); register_t tcr = READ_SYSREG(TCR_EL1); unsigned int _perms; diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 3103620323..111a2029e6 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -384,7 +384,7 @@ void panic_PAR(uint64_t par) static void cpsr_switch_mode(struct cpu_user_regs *regs, int mode) { - uint32_t sctlr = READ_SYSREG32(SCTLR_EL1); + register_t sctlr = READ_SYSREG(SCTLR_EL1); regs->cpsr &= ~(PSR_MODE_MASK|PSR_IT_MASK|PSR_JAZELLE|PSR_BIG_ENDIAN|PSR_THUMB); @@ -400,7 +400,7 @@ static void cpsr_switch_mode(struct cpu_user_regs *regs, int mode) static vaddr_t exception_handler32(vaddr_t offset) { - uint32_t sctlr = READ_SYSREG32(SCTLR_EL1); + register_t sctlr = READ_SYSREG(SCTLR_EL1); if ( sctlr & SCTLR_A32_EL1_V ) return 0xffff0000 + offset; @@ -719,7 +719,7 @@ crash_system: struct reg_ctxt { /* Guest-side state */ - uint32_t sctlr_el1; + register_t sctlr_el1; register_t tcr_el1; uint64_t ttbr0_el1, ttbr1_el1; #ifdef CONFIG_ARM_32 @@ -822,7 +822,7 @@ static void show_registers_32(const struct cpu_user_regs *regs, if ( guest_mode ) { - printk(" SCTLR: %08"PRIx32"\n", ctxt->sctlr_el1); + printk(" SCTLR: %"PRIregister"\n", ctxt->sctlr_el1); printk(" TCR: %08"PRIregister"\n", ctxt->tcr_el1); printk(" TTBR0: %016"PRIx64"\n", ctxt->ttbr0_el1); printk(" TTBR1: %016"PRIx64"\n", ctxt->ttbr1_el1); @@ -894,7 +894,7 @@ static void show_registers_64(const struct cpu_user_regs *regs, printk(" ESR_EL1: %08"PRIx32"\n", ctxt->esr_el1); printk(" FAR_EL1: %016"PRIx64"\n", ctxt->far); printk("\n"); - printk(" SCTLR_EL1: %08"PRIx32"\n", ctxt->sctlr_el1); + printk(" SCTLR_EL1: %"PRIregister"\n", ctxt->sctlr_el1); printk(" TCR_EL1: %08"PRIregister"\n", ctxt->tcr_el1); printk(" TTBR0_EL1: %016"PRIx64"\n", ctxt->ttbr0_el1); printk(" TTBR1_EL1: %016"PRIx64"\n", ctxt->ttbr1_el1); diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 2960a53e69..86ebdd2bcf 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -167,7 +167,8 @@ struct arch_vcpu #endif /* Control Registers */ - uint32_t actlr, sctlr; + register_t sctlr; + uint32_t actlr; uint32_t cpacr; uint32_t contextidr; diff --git a/xen/include/asm-arm/p2m.h b/xen/include/asm-arm/p2m.h index 2f89bb00c3..03f2ee75c1 100644 --- a/xen/include/asm-arm/p2m.h +++ b/xen/include/asm-arm/p2m.h @@ -391,12 +391,12 @@ static inline int set_foreign_p2m_entry(struct domain *d, unsigned long gfn, */ static inline bool vcpu_has_cache_enabled(struct vcpu *v) { - const uint32_t mask = SCTLR_Axx_ELx_C | SCTLR_Axx_ELx_M; + const register_t mask = SCTLR_Axx_ELx_C | SCTLR_Axx_ELx_M; /* Only works with the current vCPU */ ASSERT(current == v); - return (READ_SYSREG32(SCTLR_EL1) & mask) == mask; + return (READ_SYSREG(SCTLR_EL1) & mask) == mask; } #endif /* _XEN_P2M_H */ diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index 7ce139a0f5..d9a06efbd8 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -291,7 +291,7 @@ struct vcpu_guest_context { struct vcpu_guest_core_regs user_regs; /* Core CPU registers */ - uint32_t sctlr; + uint64_t sctlr; uint64_t ttbcr, ttbr0, ttbr1; }; typedef struct vcpu_guest_context vcpu_guest_context_t; @@ -380,7 +380,7 @@ typedef uint64_t xen_callback_t; #define PSR_GUEST32_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_SVC) #define PSR_GUEST64_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_EL1h) -#define SCTLR_GUEST_INIT 0x00c50078 +#define SCTLR_GUEST_INIT xen_mk_ullong(0x00c50078) /* * Virtual machine platform (memory layout, interrupts)