From patchwork Fri May 10 02:18:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 16849 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-yh0-f71.google.com (mail-yh0-f71.google.com [209.85.213.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 0CC6924AAB for ; Fri, 10 May 2013 02:20:21 +0000 (UTC) Received: by mail-yh0-f71.google.com with SMTP id a41sf4555311yho.6 for ; Thu, 09 May 2013 19:19:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:mime-version:x-beenthere:x-received:received-spf :x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-received:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=BPuyNE6sHu9A6Y74SozptWXu7eVpj2Jgq16cNFqHigk=; b=knonHaBKDpSEr47rzPY8Jd/PLtVtF7h+PXGqWYHfqhXL4cGj4Qlcg17sqbWbufe693 M65KqGJLPvbq6N0LpyaebwdFpoGzQWkpGq+sQL/tyE9oaImSLYZB0D9tNrEkBKymcXJz ystRSO1GyqVcLKVm3EAfoI2pR30ieZkMKPiJO87jkLXkGAEtuViv8LrI/P9layWKV0dY /1Bj+MhpL42rQxb7It5DJa5dHHBlAHXgZD2UORzjTTHBPdaH1IcqrA5uTh8IrK6DMwji CIrQIhrrWDXP0JeHjj6SjdhZDPe0icKOMRTAJujk1wwbzgPbxc3YAZd+cyGlhLO2eacG JY4w== X-Received: by 10.224.200.202 with SMTP id ex10mr11066475qab.8.1368152396375; Thu, 09 May 2013 19:19:56 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.119.129 with SMTP id ku1ls1782623qeb.49.gmail; Thu, 09 May 2013 19:19:56 -0700 (PDT) X-Received: by 10.52.94.227 with SMTP id df3mr8315024vdb.48.1368152396121; Thu, 09 May 2013 19:19:56 -0700 (PDT) Received: from mail-ve0-x22a.google.com (mail-ve0-x22a.google.com [2607:f8b0:400c:c01::22a]) by mx.google.com with ESMTPS id tq4si323519vdc.131.2013.05.09.19.19.56 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 09 May 2013 19:19:56 -0700 (PDT) Received-SPF: neutral (google.com: 2607:f8b0:400c:c01::22a is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=2607:f8b0:400c:c01::22a; Received: by mail-ve0-f170.google.com with SMTP id 15so3486500vea.15 for ; Thu, 09 May 2013 19:19:56 -0700 (PDT) X-Received: by 10.52.66.101 with SMTP id e5mr8322678vdt.57.1368152396004; Thu, 09 May 2013 19:19:56 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.217.15 with SMTP id hk15csp36254vcb; Thu, 9 May 2013 19:19:55 -0700 (PDT) X-Received: by 10.180.188.141 with SMTP id ga13mr747052wic.9.1368152394862; Thu, 09 May 2013 19:19:54 -0700 (PDT) Received: from mail-wg0-x229.google.com (mail-wg0-x229.google.com [2a00:1450:400c:c00::229]) by mx.google.com with ESMTPS id lt1si174593wjb.12.2013.05.09.19.19.54 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 09 May 2013 19:19:54 -0700 (PDT) Received-SPF: neutral (google.com: 2a00:1450:400c:c00::229 is neither permitted nor denied by best guess record for domain of julien.grall@linaro.org) client-ip=2a00:1450:400c:c00::229; Received: by mail-wg0-f41.google.com with SMTP id y10so185839wgg.2 for ; Thu, 09 May 2013 19:19:54 -0700 (PDT) X-Received: by 10.194.61.237 with SMTP id t13mr21581264wjr.2.1368152394256; Thu, 09 May 2013 19:19:54 -0700 (PDT) Received: from belegaer.uk.xensource.com. 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[46.33.159.2]) by mx.google.com with ESMTPSA id dj7sm597075wib.6.2013.05.09.19.19.52 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 09 May 2013 19:19:53 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Cc: Stefano.Stabellini@eu.citrix.com, ian.campbell@citrix.com, patches@linaro.org, Anthony PERARD , Julien Grall Subject: [PATCH V3 38/41] xen/arm: Add Exynos 4210 UART support for early printk Date: Fri, 10 May 2013 03:18:24 +0100 Message-Id: <1368152307-598-39-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1368152307-598-1-git-send-email-julien.grall@linaro.org> References: <1368152307-598-1-git-send-email-julien.grall@linaro.org> X-Gm-Message-State: ALoCoQnhC4Fic4Tf1tYm5GDCxpk7vVz3m9TM/a8B4hQDKCvYBKz5SEfK9OPjMMoTUR/H0DOwRyKK X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::22a is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Anthony PERARD Signed-off-by: Anthony PERARD Signed-off-by: Julien Grall Changes in v3: - Typoes - Remove $(CONFIG_EARLY_PL011) because of a bad merge in v2 - Remove redundant line EARLY_PRINTK :=y Changes in v2: - Use assembly macro instead of function - Add Anthony as first author Acked-by: Ian Campbell --- docs/misc/arm/early-printk.txt | 1 + xen/arch/arm/Rules.mk | 3 ++ xen/arch/arm/arm32/debug-exynos4210.inc | 77 +++++++++++++++++++++++++++++++ 3 files changed, 81 insertions(+) create mode 100644 xen/arch/arm/arm32/debug-exynos4210.inc diff --git a/docs/misc/arm/early-printk.txt b/docs/misc/arm/early-printk.txt index 4065811..d5cae85 100644 --- a/docs/misc/arm/early-printk.txt +++ b/docs/misc/arm/early-printk.txt @@ -10,5 +10,6 @@ option should not be enable for Xens that are intended to be portable. CONFIG_EARLY_PRINTK=mach where mach is the name of the machine: - vexpress: printk with pl011 for versatile express + - exynos5250: printk with the second UART By default early printk is disabled. diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk index 297385b..b6a6890 100644 --- a/xen/arch/arm/Rules.mk +++ b/xen/arch/arm/Rules.mk @@ -46,6 +46,9 @@ ifeq ($(debug),y) ifeq ($(CONFIG_EARLY_PRINTK), vexpress) EARLY_PRINTK_INC := pl011 endif +ifeq ($(CONFIG_EARLY_PRINTK), exynos5250) +EARLY_PRINTK_INC := exynos4210 +endif ifneq ($(EARLY_PRINTK_INC),) EARLY_PRINTK := y diff --git a/xen/arch/arm/arm32/debug-exynos4210.inc b/xen/arch/arm/arm32/debug-exynos4210.inc new file mode 100644 index 0000000..4241640 --- /dev/null +++ b/xen/arch/arm/arm32/debug-exynos4210.inc @@ -0,0 +1,77 @@ +/* + * xen/arch/arm/arm32/debug-exynos4210.inc + * + * Exynos 5 specific debug code + * + * Copyright (c) 2013 Citrix Systems. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define EARLY_UART_BASE_ADDRESS 0x12c20000 + +/* Exynos 5 UART initialization + * rb: register which contains the UART base address + * rc: scratch register 1 + * rd: scratch register 2 */ +.macro early_uart_init rb rc rd + /* init clock */ + ldr \rc, =0x10020000 + /* select MPLL (800MHz) source clock */ + ldr \rd, [\rc, #0x250] + and \rd, \rd, #(~(0xf<<8)) + orr \rd, \rd, #(0x6<<8) + str \rd, [\rc, #0x250] + /* ratio 800/(7+1) */ + ldr \rd, [\rc, #0x558] + and \rd, \rd, #(~(0xf<<8)) + orr \rd, \rd, #(0x7<<8) + str \rd, [\rc, #0x558] + + mov \rc, #4 + str \rc, [\rb, #UFRACVAL] /* -> UFRACVAL (Baud divisor fraction) */ + mov \rc, #53 + str \rc, [\rb, #UBRDIV] /* -> UBRDIV (Baud divisor integer) */ + mov \rc, #3 /* 8n1 */ + str \rc, [\rb, #ULCON] /* -> (Line control) */ + ldr \rc, =UCON_TX_IRQ /* TX IRQMODE */ + str \rc, [\rb, #UCON] /* -> (Control Register) */ + mov \rc, #0x0 + str \rc, [\rb, #UFCON] /* disable FIFO */ + mov \rc, #0x0 + str \rc, [\rb, #UMCON] /* no auto flow control */ +.endm + +/* Exynos 5 UART wait UART to be ready to transmit + * rb: register which contains the UART base address + * rc: scratch register */ +.macro early_uart_ready rb rc +1: + ldr \rc, [\rb, #UTRSTAT] /* <- UTRSTAT (Flag register) */ + tst \rc, #UTRSTAT_TX_EMPTY /* Check BUSY bit */ + beq 1b /* Wait for the UART to be ready */ +.endm + +/* Exynos 5 UART transmit character + * rb: register which contains the UART base address + * rt: register which contains the character to transmit */ +.macro early_uart_transmit rb rt + str \rt, [\rb, #UTXH] /* -> UTXH (Data Register) */ +.endm + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */