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[92.224.198.135]) by mx.google.com with ESMTPSA id eq4sm38120532obb.5.2013.06.13.04.08.24 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 13 Jun 2013 04:08:24 -0700 (PDT) From: Andre Przywara To: patches@linaro.org Subject: [PATCH v2 1/7] ARM: prepare armv7.h to be included from assembly source Date: Thu, 13 Jun 2013 13:07:37 +0200 Message-Id: <1371121663-18810-2-git-send-email-andre.przywara@linaro.org> X-Mailer: git-send-email 1.7.12.1 In-Reply-To: <1371121663-18810-1-git-send-email-andre.przywara@linaro.org> References: <1371121663-18810-1-git-send-email-andre.przywara@linaro.org> X-Gm-Message-State: ALoCoQlMQ2fFMmX86/4mXnlyFuOU/MILz51ToGDKZNsNUPfLfIeGCqGXqk/pERFtZC4/z6lBmc5t X-Original-Sender: andre.przywara@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::22e is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , armv7.h contains some useful constants, but also C prototypes. To include it also in assembly files, protect the non-assembly part appropriately. Signed-off-by: Andre Przywara --- arch/arm/include/asm/armv7.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index a73630b..20caa7c 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -23,7 +23,6 @@ */ #ifndef ARMV7_H #define ARMV7_H -#include /* Cortex-A9 revisions */ #define MIDR_CORTEX_A9_R0P1 0x410FC091 @@ -57,6 +56,9 @@ #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 #define ARMV7_CLIDR_CTYPE_UNIFIED 4 +#ifndef __ASSEMBLY__ +#include + /* * CP15 Barrier instructions * Please note that we have separate barrier instructions in ARMv7 @@ -74,4 +76,6 @@ void v7_outer_cache_inval_all(void); void v7_outer_cache_flush_range(u32 start, u32 end); void v7_outer_cache_inval_range(u32 start, u32 end); +#endif /* ! __ASSEMBLY__ */ + #endif