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[50.57.142.19]) by mx.google.com with ESMTPS id fj7si5365957vcb.13.2014.09.09.09.25.49 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 09 Sep 2014 09:25:50 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XROCn-0003Kt-LE; Tue, 09 Sep 2014 16:23:45 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XROCl-0003KU-NO for xen-devel@lists.xen.org; Tue, 09 Sep 2014 16:23:43 +0000 Received: from [85.158.139.211:23080] by server-5.bemta-5.messagelabs.com id D3/8D-11546-E892F045; Tue, 09 Sep 2014 16:23:42 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-10.tower-206.messagelabs.com!1410279819!8114148!2 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 10213 invoked from network); 9 Sep 2014 16:23:42 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-10.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 9 Sep 2014 16:23:42 -0000 X-IronPort-AV: E=Sophos;i="5.04,492,1406592000"; d="scan'208";a="170606690" Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.3.181.6; Tue, 9 Sep 2014 12:23:12 -0400 Received: from drall.uk.xensource.com ([10.80.16.71]) by ukmail1.uk.xensource.com with smtp (Exim 4.69) (envelope-from ) id 1XROCF-0001uN-2X; Tue, 09 Sep 2014 17:23:12 +0100 Received: by drall.uk.xensource.com (sSMTP sendmail emulation); Tue, 09 Sep 2014 17:23:11 +0100 From: Ian Campbell To: Date: Tue, 9 Sep 2014 17:23:02 +0100 Message-ID: <1410279788-27167-3-git-send-email-ian.campbell@citrix.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1410279730.8217.238.camel@kazak.uk.xensource.com> References: <1410279730.8217.238.camel@kazak.uk.xensource.com> MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH 3/9] xen: arm: Handle 32-bit EL0 on 64-bit EL1 when advancing PC after trap X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Signed-off-by: Ian Campbell Reviewed-by: Julien Grall --- xen/arch/arm/traps.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 1b1d29f..353e38e 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1370,7 +1370,7 @@ static int check_conditional_instr(struct cpu_user_regs *regs, union hsr hsr) { unsigned long it; - BUG_ON( !is_32bit_domain(current->domain) || !(cpsr&PSR_THUMB) ); + BUG_ON( !psr_mode_is_32bit(regs->cpsr) || !(cpsr&PSR_THUMB) ); it = ( (cpsr >> (10-2)) & 0xfc) | ((cpsr >> 25) & 0x3 ); @@ -1379,7 +1379,7 @@ static int check_conditional_instr(struct cpu_user_regs *regs, union hsr hsr) return 1; /* The cond for this instruction works out as the top 4 bits. */ - cond = ( it >> 4 ); + cond = ( it >> 4 ); } cpsr_cond = cpsr >> 28; @@ -1395,10 +1395,10 @@ static void advance_pc(struct cpu_user_regs *regs, union hsr hsr) unsigned long itbits, cond, cpsr = regs->cpsr; /* PSR_IT_MASK bits can only be set for 32-bit processors in Thumb mode. */ - BUG_ON( (!is_32bit_domain(current->domain)||!(cpsr&PSR_THUMB)) + BUG_ON( (!psr_mode_is_32bit(cpsr)||!(cpsr&PSR_THUMB)) && (cpsr&PSR_IT_MASK) ); - if ( is_32bit_domain(current->domain) && (cpsr&PSR_IT_MASK) ) + if ( cpsr&PSR_IT_MASK ) { /* The ITSTATE[7:0] block is contained in CPSR[15:10],CPSR[26:25] *