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[50.57.142.19]) by mx.google.com with ESMTPS id q9si15713818qab.111.2014.09.09.09.27.13 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 09 Sep 2014 09:27:13 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XROEy-0003rP-Iu; Tue, 09 Sep 2014 16:26:00 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XROEx-0003qn-PP for xen-devel@lists.xen.org; Tue, 09 Sep 2014 16:26:00 +0000 Received: from [85.158.139.211:38671] by server-6.bemta-5.messagelabs.com id 7B/E0-06284-61A2F045; Tue, 09 Sep 2014 16:25:58 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-7.tower-206.messagelabs.com!1410279955!13474798!2 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 27480 invoked from network); 9 Sep 2014 16:25:58 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-7.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 9 Sep 2014 16:25:58 -0000 X-IronPort-AV: E=Sophos;i="5.04,492,1406592000"; d="scan'208";a="169814310" Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.3.181.6; Tue, 9 Sep 2014 12:23:13 -0400 Received: from drall.uk.xensource.com ([10.80.16.71]) by ukmail1.uk.xensource.com with smtp (Exim 4.69) (envelope-from ) id 1XROCG-0001uQ-3v; Tue, 09 Sep 2014 17:23:13 +0100 Received: by drall.uk.xensource.com (sSMTP sendmail emulation); Tue, 09 Sep 2014 17:23:12 +0100 From: Ian Campbell To: Date: Tue, 9 Sep 2014 17:23:03 +0100 Message-ID: <1410279788-27167-4-git-send-email-ian.campbell@citrix.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1410279730.8217.238.camel@kazak.uk.xensource.com> References: <1410279730.8217.238.camel@kazak.uk.xensource.com> MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH 4/9] xen: arm: turn vtimer traps for cp32/64 and sysreg into #undef X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: We have allowed EL1 to access these registers directly for some time (at least since 4.3.0). They were only ever trapped to support very early models which had a buggy hypervisor timer, requiring us to use the phys timer for Xen itself. In the interests of minimising the patch for the security update just remove the call to vtimer_emulate and inject an #undef exception. In practice we will never see any of these traps. Handle CNTPCT_EL0 explicitly for consistency with CNTPCT on 32-bit. Signed-off-by: Ian Campbell --- xen/arch/arm/traps.c | 37 ++++++++++++------------------------- 1 file changed, 12 insertions(+), 25 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 353e38e..46ed21d 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1478,13 +1478,8 @@ static void do_cp15_32(struct cpu_user_regs *regs, break; case HSR_CPREG32(CNTP_CTL): case HSR_CPREG32(CNTP_TVAL): - if ( !vtimer_emulate(regs, hsr) ) - { - dprintk(XENLOG_ERR, - "failed emulation of 32-bit vtimer CP register access\n"); - domain_crash_synchronous(); - } - break; + goto undef_cp15_32; + case HSR_CPREG32(ACTLR): if ( cp32.read ) *r = v->arch.actlr; @@ -1526,6 +1521,7 @@ static void do_cp15_32(struct cpu_user_regs *regs, gdprintk(XENLOG_ERR, "unhandled 32-bit CP15 access %#x\n", hsr.bits & HSR_CP32_REGS_MASK); #endif + undef_cp15_32: inject_undef_exception(regs, hsr.len); return; } @@ -1544,13 +1540,8 @@ static void do_cp15_64(struct cpu_user_regs *regs, switch ( hsr.bits & HSR_CP64_REGS_MASK ) { case HSR_CPREG64(CNTPCT): - if ( !vtimer_emulate(regs, hsr) ) - { - dprintk(XENLOG_ERR, - "failed emulation of 64-bit vtimer CP register access\n"); - domain_crash_synchronous(); - } - break; + goto undef_cp15_64; + default: { #ifndef NDEBUG @@ -1563,6 +1554,7 @@ static void do_cp15_64(struct cpu_user_regs *regs, gdprintk(XENLOG_ERR, "unhandled 64-bit CP15 access %#x\n", hsr.bits & HSR_CP64_REGS_MASK); #endif + undef_cp15_64: inject_undef_exception(regs, hsr.len); return; } @@ -1729,18 +1721,13 @@ static void do_sysreg(struct cpu_user_regs *regs, break; case HSR_SYSREG_CNTP_CTL_EL0: case HSR_SYSREG_CNTP_TVAL_EL0: - if ( !vtimer_emulate(regs, hsr) ) - { - dprintk(XENLOG_ERR, - "failed emulation of 64-bit vtimer sysreg access\n"); - domain_crash_synchronous(); - } - break; + case HSR_SYSREG_CNTPCT_EL0: + goto undef_sysreg; default: bad_sysreg: { - struct hsr_sysreg sysreg = hsr.sysreg; #ifndef NDEBUG + struct hsr_sysreg sysreg = hsr.sysreg; gdprintk(XENLOG_ERR, "%s %d, %d, c%d, c%d, %d %s x%d @ 0x%"PRIregister"\n", @@ -1753,7 +1740,8 @@ static void do_sysreg(struct cpu_user_regs *regs, gdprintk(XENLOG_ERR, "unhandled 64-bit sysreg access %#x\n", hsr.bits & HSR_SYSREG_REGS_MASK); #endif - inject_undef_exception(regs, sysreg.len); + undef_sysreg: + inject_undef_exception(regs, hsr.len); return; } } @@ -1925,8 +1913,7 @@ asmlinkage void do_trap_hypervisor(struct cpu_user_regs *regs) do_cp15_32(regs, hsr); break; case HSR_EC_CP15_64: - if ( !is_32bit_domain(current->domain) ) - goto bad_trap; + BUG_ON(!psr_mode_is_32bit(regs->cpsr)); do_cp15_64(regs, hsr); break; case HSR_EC_CP14_32: