From patchwork Mon Mar 7 11:52:16 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 401 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:42:21 -0000 Delivered-To: patches@linaro.org Received: by 10.224.60.68 with SMTP id o4cs96163qah; Mon, 7 Mar 2011 03:52:20 -0800 (PST) Received: by 10.52.69.36 with SMTP id b4mr5306403vdu.240.1299498740702; Mon, 07 Mar 2011 03:52:20 -0800 (PST) Received: from mail.codesourcery.com (mail.codesourcery.com [38.113.113.100]) by mx.google.com with ESMTPS id v19si1015744vdt.109.2011.03.07.03.52.19 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 07 Mar 2011 03:52:19 -0800 (PST) Received-SPF: pass (google.com: domain of ams@codesourcery.com designates 38.113.113.100 as permitted sender) client-ip=38.113.113.100; Authentication-Results: mx.google.com; spf=pass (google.com: domain of ams@codesourcery.com designates 38.113.113.100 as permitted sender) smtp.mail=ams@codesourcery.com Received: (qmail 30668 invoked from network); 7 Mar 2011 11:52:18 -0000 Received: from unknown (HELO ?192.168.0.104?) (ams@127.0.0.2) by mail.codesourcery.com with ESMTPA; 7 Mar 2011 11:52:18 -0000 Message-ID: <4D74C6F0.6020901@codesourcery.com> Date: Mon, 07 Mar 2011 11:52:16 +0000 From: Andrew Stubbs Organization: CodeSourcery User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.14) Gecko/20110223 Lightning/1.0b2 Thunderbird/3.1.8 MIME-Version: 1.0 To: patches@linaro.org Subject: Fwd: [PATCH][ARM] Tweak arm_class_likely_spilled_p, MODE_BASE_REG_CLASS for Thumb-2 -------- Original Message -------- Subject: [PATCH][ARM] Tweak arm_class_likely_spilled_p, MODE_BASE_REG_CLASS for Thumb-2 Date: Mon, 14 Feb 2011 14:20:43 +0000 From: Andrew Stubbs Organization: CodeSourcery To: gcc-patches@gcc.gnu.org This patch is a rework of an old one: http://gcc.gnu.org/ml/gcc-patches/2010-06/msg01080.html The ARM parts of that patch were approved, but the target independent parts were never reviewed (AFAICT), and the patch no longer applies. I've updated the target-specific parts. As far as I can tell, the target independent parts are no longer required, so I've dropped them. Tested with no regressions for ARM mode and Thumb2 mode. OK? Andrew 2011-02-14 Andrew Stubbs Julian Brown Mark Shinwell gcc/ * config/arm/arm.h (arm_class_likely_spilled_p): Check against LO_REGS only for Thumb-1. (MODE_BASE_REG_CLASS): Restrict base registers to those which can be used in short instructions when optimising for size on Thumb-2. --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -22304,14 +22304,16 @@ arm_preferred_simd_mode (enum machine_mode mode) /* Implement TARGET_CLASS_LIKELY_SPILLED_P. - We need to define this for LO_REGS on thumb. Otherwise we can end up - using r0-r4 for function arguments, r7 for the stack frame and don't - have enough left over to do doubleword arithmetic. */ - + We need to define this for LO_REGS on Thumb-1. Otherwise we can end up + using r0-r4 for function arguments, r7 for the stack frame and don't have + enough left over to do doubleword arithmetic. For Thumb-2 all the + potentially problematic instructions accept high registers so this is not + necessary. Care needs to be taken to avoid adding new Thumb-2 patterns + that require many low registers. */ static bool arm_class_likely_spilled_p (reg_class_t rclass) { - if ((TARGET_THUMB && rclass == LO_REGS) + if ((TARGET_THUMB1 && rclass == LO_REGS) || rclass == CC_REG) return true; --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1185,7 +1185,7 @@ enum reg_class when addressing quantities in QI or HI mode; if we don't know the mode, then we must be conservative. */ #define MODE_BASE_REG_CLASS(MODE) \ - (TARGET_32BIT ? CORE_REGS : \ + (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \ (((MODE) == SImode) ? BASE_REGS : LO_REGS)) /* For Thumb we can not support SP+reg addressing, so we return LO_REGS