From patchwork Sun Apr 28 23:02:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 16492 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-yh0-f72.google.com (mail-yh0-f72.google.com [209.85.213.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 1439B2395E for ; Sun, 28 Apr 2013 23:03:54 +0000 (UTC) Received: by mail-yh0-f72.google.com with SMTP id f35sf8596719yha.7 for ; Sun, 28 Apr 2013 16:02:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:mime-version:x-beenthere:x-received:received-spf :x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-received:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=iUwX2RKnX4kGU8GKYaKryC3aWDiictjeVsTYb5QTBys=; b=DytiSEKu7O4tKWi2/og3JgqoYqIS79NQfj6LN6enmALhuBog+ffzdbXins4RI6LA7t QszKD48ky6lWp9506jDR8aTL5cmHTiPD09mRz39rDmi3Yl+6/9Wj4rdoJ4/KW/Ztkefm ctp70xdHqI+sEGrnif9fXIJbQ8uscFEgtqrvqwWJGu7k4JpZ3LLNcTLHsXSGcBvk3qQb O9GnkYOKiGtKIqxRblFbVxVs4yZDBxpo3G0Xb15i907ikvqLWIvaZOA3fJwSpYIWZBbm 5DDgfiqRstp/POc/qkv56U+SkIbrRE5/12Vm+8Eu7SXH3snvonA2i1oOkKN6XoRv4XZg HqCw== X-Received: by 10.224.36.66 with SMTP id s2mr4938640qad.6.1367190172926; Sun, 28 Apr 2013 16:02:52 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.35.238 with SMTP id l14ls41124qej.13.gmail; Sun, 28 Apr 2013 16:02:52 -0700 (PDT) X-Received: by 10.59.9.39 with SMTP id dp7mr32427190ved.36.1367190172734; Sun, 28 Apr 2013 16:02:52 -0700 (PDT) Received: from mail-vb0-x22f.google.com (mail-vb0-x22f.google.com [2607:f8b0:400c:c02::22f]) by mx.google.com with ESMTPS id e5si8945426vcu.88.2013.04.28.16.02.52 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 28 Apr 2013 16:02:52 -0700 (PDT) Received-SPF: neutral (google.com: 2607:f8b0:400c:c02::22f is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=2607:f8b0:400c:c02::22f; Received: by mail-vb0-f47.google.com with SMTP id x14so202721vbb.6 for ; Sun, 28 Apr 2013 16:02:52 -0700 (PDT) X-Received: by 10.52.166.103 with SMTP id zf7mr27601677vdb.94.1367190172449; Sun, 28 Apr 2013 16:02:52 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.58.127.98 with SMTP id nf2csp33810veb; Sun, 28 Apr 2013 16:02:51 -0700 (PDT) X-Received: by 10.194.71.241 with SMTP id y17mr7230046wju.31.1367190171475; Sun, 28 Apr 2013 16:02:51 -0700 (PDT) Received: from mail-we0-x229.google.com (mail-we0-x229.google.com [2a00:1450:400c:c03::229]) by mx.google.com with ESMTPS id iy12si3190376wic.106.2013.04.28.16.02.51 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 28 Apr 2013 16:02:51 -0700 (PDT) Received-SPF: neutral (google.com: 2a00:1450:400c:c03::229 is neither permitted nor denied by best guess record for domain of julien.grall@linaro.org) client-ip=2a00:1450:400c:c03::229; Received: by mail-we0-f169.google.com with SMTP id p43so5189187wea.28 for ; Sun, 28 Apr 2013 16:02:51 -0700 (PDT) X-Received: by 10.180.183.133 with SMTP id em5mr14019062wic.26.1367190171093; Sun, 28 Apr 2013 16:02:51 -0700 (PDT) Received: from belegaer.uk.xensource.com. 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[46.33.159.2]) by mx.google.com with ESMTPSA id k5sm18711393wiy.5.2013.04.28.16.02.49 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 28 Apr 2013 16:02:50 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Cc: ian.campbell@citrix.com, patches@linaro.org, anthony.perard@citrix.com, stefano.stabellini@eu.citrix.com, Julien Grall Subject: [RFC 26/29] xen/arm: Add Exynos 4210 UART support for early printk Date: Mon, 29 Apr 2013 00:02:09 +0100 Message-Id: X-Mailer: git-send-email 1.7.10.4 In-Reply-To: References: X-Gm-Message-State: ALoCoQkc4TvKIH0r5jbFQ+wkWbTyM5NXxFNA4nNRw0dtpsTo2JMQjJ5FVLzsX0ZmFveqwGUDwDOL X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c02::22f is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Signed-off-by: Julien Grall --- config/arm32.mk | 1 + xen/arch/arm/Rules.mk | 4 ++ xen/arch/arm/arm32/Makefile | 1 + xen/arch/arm/arm32/debug-exynos5.S | 81 ++++++++++++++++++++++++++++++++++++ 4 files changed, 87 insertions(+) create mode 100644 xen/arch/arm/arm32/debug-exynos5.S diff --git a/config/arm32.mk b/config/arm32.mk index 593a1d1..01c1490 100644 --- a/config/arm32.mk +++ b/config/arm32.mk @@ -17,6 +17,7 @@ CFLAGS += -marm # Possible value: # - none: no early printk # - pl011: printk with PL011 UART +# - exynos5: printk with the second exynos 5 UART CONFIG_EARLY_PRINTK := none HAS_PL011 := y HAS_EXYNOS5 := y diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk index 2053b1e..7dcc0b7 100644 --- a/xen/arch/arm/Rules.mk +++ b/xen/arch/arm/Rules.mk @@ -43,5 +43,9 @@ ifeq ($(CONFIG_EARLY_PRINTK), pl011) EARLY_PRINTK := y CONFIG_EARLY_PL011 := y endif +ifeq ($(CONFIG_EARLY_PRINTK), exynos5) +EARLY_PRINTK := y +CONFIG_EARLY_EXYNOS5 := y +endif CFLAGS-$(EARLY_PRINTK) += -DEARLY_PRINTK diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile index 6af8ca3..90e4eab 100644 --- a/xen/arch/arm/arm32/Makefile +++ b/xen/arch/arm/arm32/Makefile @@ -9,3 +9,4 @@ obj-y += domain.o obj-$(EARLY_PRINTK) += debug.o obj-$(CONFIG_EARLY_PL011) += debug-pl011.o +obj-$(CONFIG_EARLY_EXYNOS5) += debug-exynos5.o diff --git a/xen/arch/arm/arm32/debug-exynos5.S b/xen/arch/arm/arm32/debug-exynos5.S new file mode 100644 index 0000000..cbe1705 --- /dev/null +++ b/xen/arch/arm/arm32/debug-exynos5.S @@ -0,0 +1,81 @@ +/* + * xen/arch/arm/arm32/debug-exynos5.S + * + * Exynos 5 specific debug code + * + * Copyright (c) 2013 Citrix Systems. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#define EXYNOS5_UART_BASE_ADDRESS 0x12c20000 + +.globl early_uart_paddr +early_uart_paddr: .word EXYNOS5_UART_BASE_ADDRESS + +/* Exynos 5 UART initialization + * r11: UART base address + * Clobber r0-r1 */ +.globl early_uart_init +early_uart_init: + /* init clock */ + ldr r1, =0x10020000 + /* select MPLL (800MHz) source clock */ + ldr r0, [r1, #0x250] + and r0, r0, #(~(0xf<<8)) + orr r0, r0, #(0x6<<8) + str r0, [r1, #0x250] + /* ration 800/(7+1) */ + ldr r0, [r1, #0x558] + and r0, r0, #(~(0xf<<8)) + orr r0, r0, #(0x7<<8) + str r0, [r1, #0x558] + + mov r1, #4 + str r1, [r11, #0x2c] /* -> UARTIBRD (Baud divisor fraction) */ + mov r1, #53 + str r1, [r11, #0x28] /* -> UARTIBRD (Baud divisor integer) */ + mov r1, #3 /* 8n1 */ + str r1, [r11, #0x0] /* -> (Line control) */ + ldr r1, =(1<<2) /* TX IRQMODE */ + str r1, [r11, #0x4] /* -> (Control Register) */ + mov r1, #0x0 + str r1, [r11, #0x8] /* disable FIFO */ + mov r1, #0x0 + str r1, [r11, #0x0C] /* no auto flow control */ + mov pc, lr + +/* Exynos 5 UART wait UART to be ready to transmit + * r11: UART base address + * Clobber r2 r11 */ +.globl early_uart_ready +early_uart_ready: + ldr r2, [r11, #0x10] /* <- UTRSTAT (Flag register) */ + tst r2, #(1<<1) /* Check BUSY bit */ + beq early_uart_ready /* Wait for the UART to be ready */ + mov pc, lr + +/* Exynos 5 UART transmit character + * r2: character to transmit + * r11: UART base address */ +.globl early_uart_transmit +early_uart_transmit: + str r2, [r11, #0x20] /* -> UTXH (Data Register) */ + mov pc, lr + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */