mbox series

[PULL,00/22] target-arm queue

Message ID 1485531137-2362-1-git-send-email-peter.maydell@linaro.org
Headers show
Series target-arm queue | expand

Message

Peter Maydell Jan. 27, 2017, 3:31 p.m. UTC 
ARM queue; the bulk of this is M profile bugfixes.

thanks
-- PMM

The following changes since commit 8a26d88507b51b7cc5dc40732e51ccc135fec0f6:

  Merge remote-tracking branch 'remotes/berrange/tags/pull-qio-2017-01-26-1' into staging (2017-01-27 14:08:57 +0000)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170127

for you to fetch changes up to 146871c33eb70ca7090a0a55e69e5a8f9b5eb102:

  dma: omap: check dma channel data_type (2017-01-27 15:29:08 +0000)

----------------------------------------------------------------
target-arm queue:
 * various minor M profile bugfixes
 * aspeed/smc: handle dummy bytes when doing fast reads in command mode
 * pflash_cfi01: fix per-device sector length in CFI table
 * arm: stellaris: make MII accesses complete immediately
 * hw/char/exynos4210_uart: Drop unused local variable frame_size
 * arm_gicv3: Fix broken logic in ELRSR calculation
 * dma: omap: check dma channel data_type

----------------------------------------------------------------
Cédric Le Goater (1):
      aspeed/smc: handle dummy bytes when doing fast reads in command mode

Michael Davidsaver (12):
      armv7m: MRS/MSR: handle unprivileged access
      armv7m: Replace armv7m.hack with unassigned_access handler
      armv7m: Explicit error for bad vector table
      armv7m: Fix reads of CONTROL register bit 1
      armv7m: Clear FAULTMASK on return from non-NMI exceptions
      armv7m_nvic: keep a pointer to the CPU
      armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR
      armv7m: honour CCR.STACKALIGN on exception entry
      armv7m: set CFSR.UNDEFINSTR on undefined instructions
      armv7m: Honour CCR.USERSETMPEND
      armv7m: FAULTMASK should be 0 on reset
      arm: stellaris: make MII accesses complete immediately

Peter Maydell (8):
      hw/registerfields.h: Pull FIELD etc macros out of hw/register.h
      pflash_cfi01: fix per-device sector length in CFI table
      target/arm: Drop IS_M() macro
      armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR
      armv7m: Report no-coprocessor faults correctly
      armv7m: R14 should reset to 0xffffffff
      hw/char/exynos4210_uart: Drop unused local variable frame_size
      arm_gicv3: Fix broken logic in ELRSR calculation

Prasad J Pandit (1):
      dma: omap: check dma channel data_type

 include/hw/compat.h         |   4 ++
 include/hw/register.h       |  47 +------------
 include/hw/registerfields.h |  60 +++++++++++++++++
 target/arm/cpu.h            |  62 +++++++++++++++--
 target/arm/internals.h      |   7 ++
 hw/arm/armv7m.c             |   8 ---
 hw/block/pflash_cfi01.c     |  22 ++++--
 hw/char/exynos4210_uart.c   |   6 +-
 hw/dma/omap_dma.c           |  10 ++-
 hw/intc/arm_gicv3_cpuif.c   |   2 +-
 hw/intc/armv7m_nvic.c       |  58 +++++++++++-----
 hw/net/stellaris_enet.c     |   5 +-
 hw/ssi/aspeed_smc.c         |  21 ++++++
 linux-user/main.c           |   1 +
 target/arm/cpu.c            |  50 ++++++++++++--
 target/arm/helper.c         | 160 +++++++++++++++++++++++++++-----------------
 target/arm/machine.c        |  12 ++--
 target/arm/translate.c      |  20 ++++--
 18 files changed, 386 insertions(+), 169 deletions(-)
 create mode 100644 include/hw/registerfields.h

Comments

no-reply@patchew.org Jan. 27, 2017, 4:12 p.m. UTC | #1 
Hi,

Your series seems to have some coding style problems. See output below for
more information:

Type: series
Subject: [Qemu-devel] [PULL 00/22] target-arm queue
Message-id: 1485531137-2362-1-git-send-email-peter.maydell@linaro.org

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/1485447262-27014-1-git-send-email-mst@redhat.com -> patchew/1485447262-27014-1-git-send-email-mst@redhat.com
 * [new tag]         patchew/1485531137-2362-1-git-send-email-peter.maydell@linaro.org -> patchew/1485531137-2362-1-git-send-email-peter.maydell@linaro.org
Switched to a new branch 'test'
51b769b dma: omap: check dma channel data_type
f9f7f1b arm_gicv3: Fix broken logic in ELRSR calculation
55b3d0c hw/char/exynos4210_uart: Drop unused local variable frame_size
a18e1b9 arm: stellaris: make MII accesses complete immediately
19ff761 armv7m: R14 should reset to 0xffffffff
c825a48 armv7m: FAULTMASK should be 0 on reset
44c8660 armv7m: Honour CCR.USERSETMPEND
a868e15 armv7m: Report no-coprocessor faults correctly
f76a2fa armv7m: set CFSR.UNDEFINSTR on undefined instructions
7b16c2e armv7m: honour CCR.STACKALIGN on exception entry
5b10d87 armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR
275e822 armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR
16dcdc1 armv7m_nvic: keep a pointer to the CPU
3dc52da target/arm: Drop IS_M() macro
e6c3816 pflash_cfi01: fix per-device sector length in CFI table
f83ac4e armv7m: Clear FAULTMASK on return from non-NMI exceptions
b62c642 armv7m: Fix reads of CONTROL register bit 1
698250d hw/registerfields.h: Pull FIELD etc macros out of hw/register.h
07c53ea armv7m: Explicit error for bad vector table
7acb50c armv7m: Replace armv7m.hack with unassigned_access handler
eb2c228 armv7m: MRS/MSR: handle unprivileged access
c1d24d5 aspeed/smc: handle dummy bytes when doing fast reads in command mode

=== OUTPUT BEGIN ===
Checking PATCH 1/22: aspeed/smc: handle dummy bytes when doing fast reads in command mode...
Checking PATCH 2/22: armv7m: MRS/MSR: handle unprivileged access...
Checking PATCH 3/22: armv7m: Replace armv7m.hack with unassigned_access handler...
Checking PATCH 4/22: armv7m: Explicit error for bad vector table...
Checking PATCH 5/22: hw/registerfields.h: Pull FIELD etc macros out of hw/register.h...
ERROR: Macros with multiple statements should be enclosed in a do - while loop
#112: FILE: include/hw/registerfields.h:19:
+#define REG32(reg, addr)                                                  \
+    enum { A_ ## reg = (addr) };                                          \
+    enum { R_ ## reg = (addr) / 4 };

ERROR: trailing whitespace
#118: FILE: include/hw/registerfields.h:25:
+/* This macro will define FOO_BAR_MASK, FOO_BAR_SHIFT and FOO_BAR_LENGTH $

ERROR: Macros with multiple statements should be enclosed in a do - while loop
#121: FILE: include/hw/registerfields.h:28:
+#define FIELD(reg, field, shift, length)                                  \
+    enum { R_ ## reg ## _ ## field ## _SHIFT = (shift)};                  \
+    enum { R_ ## reg ## _ ## field ## _LENGTH = (length)};                \
+    enum { R_ ## reg ## _ ## field ## _MASK =                             \
+                                        MAKE_64BIT_MASK(shift, length)};

total: 3 errors, 0 warnings, 117 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 6/22: armv7m: Fix reads of CONTROL register bit 1...
Checking PATCH 7/22: armv7m: Clear FAULTMASK on return from non-NMI exceptions...
Checking PATCH 8/22: pflash_cfi01: fix per-device sector length in CFI table...
Checking PATCH 9/22: target/arm: Drop IS_M() macro...
Checking PATCH 10/22: armv7m_nvic: keep a pointer to the CPU...
Checking PATCH 11/22: armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR...
Checking PATCH 12/22: armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR...
Checking PATCH 13/22: armv7m: honour CCR.STACKALIGN on exception entry...
Checking PATCH 14/22: armv7m: set CFSR.UNDEFINSTR on undefined instructions...
Checking PATCH 15/22: armv7m: Report no-coprocessor faults correctly...
Checking PATCH 16/22: armv7m: Honour CCR.USERSETMPEND...
Checking PATCH 17/22: armv7m: FAULTMASK should be 0 on reset...
Checking PATCH 18/22: armv7m: R14 should reset to 0xffffffff...
Checking PATCH 19/22: arm: stellaris: make MII accesses complete immediately...
Checking PATCH 20/22: hw/char/exynos4210_uart: Drop unused local variable frame_size...
Checking PATCH 21/22: arm_gicv3: Fix broken logic in ELRSR calculation...
Checking PATCH 22/22: dma: omap: check dma channel data_type...
=== OUTPUT END ===

Test command exited with code: 1


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Peter Maydell Jan. 30, 2017, 10:23 a.m. UTC | #2 
On 27 January 2017 at 15:31, Peter Maydell <peter.maydell@linaro.org> wrote:
> ARM queue; the bulk of this is M profile bugfixes.

>

> thanks

> -- PMM


Applied, thanks.

-- PMM