From patchwork Tue Aug 22 15:08:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 110665 Delivered-To: patches@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2815935qge; Tue, 22 Aug 2017 08:08:58 -0700 (PDT) X-Received: by 10.28.203.78 with SMTP id b75mr4257wmg.50.1503414538575; Tue, 22 Aug 2017 08:08:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503414538; cv=none; d=google.com; s=arc-20160816; b=XR4HpRqm//755RT4u1nS8CJv+nB52gLu33yM9tQW3/19Lx+C5qlthbEPLBfFMGixz2 EVlr+Db8bX62iGD2RBED7N+TaGVjIlhy093NhR26Y3RHLEDHNsCFEyBMGc0sgFduPi4v lHwArV9k08qR3Q6a0+WT3URtVt/JXMkKgfLIFxY6VHdRMxRnZNSI7GaQUUAabK0A+PmV u0w+tDtBXCLhEtPhIJBRF5g/iuiRiG354hAymIw+0+fpJ/wX0OX1rAUdf9qj8zyToAg2 QK+rr/UsFp/bkvRB/70DAW0JfLGe9HABMeLp4NaPITCh8kvECaTSWEU948mS6IQIIKYy +diw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=message-id:date:subject:cc:to:from:arc-authentication-results; bh=hz4KQZwOGryrU5tGLJV4YLT8MuGG1TLM1gG7oVsvXiY=; b=lWQX+jGUkm0wEMu6u8OIGWANlHGu9fJoELJAcb/GOEXftcVdG/ldrod3LZ2Ht2UYzL GyveMf2UBankpWvAy9baWLHH0Tg2eBUNDO0mvCASLtpyWNbAWgWn9ZqeTkMTbqrc8E64 nuBo4vAgG+k8id7qE1yDh/KHUW9XaoFxw+5ZE6TSugZaU61hAHGLfO3IqC/H4xisimmc gTFrfarcg1r7QIT72nvUMtUq3NVhShRvEE4Nypgit2pLdj0uhthuGe9b4VJrEoeqDBVf 4nJfh1lMnPScWBTWKHnGI/k/HVLzexv62aToqpH6prtutQleSVDsProClWcUmZoReA+j rwFg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 92si1338401wrq.350.2017.08.22.08.08.58 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Aug 2017 08:08:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnZ-0004dW-5g; Tue, 22 Aug 2017 16:08:57 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 00/20] first steps towards v8M support Date: Tue, 22 Aug 2017 16:08:39 +0100 Message-Id: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 Hi; this patchset is the first slice of work aiming at support of the ARM v8M architecture. It doesn't do anything by itself (there's no CPU yet that enables the new feature) and there's a lot more work still to do to get something actually functional, but it seems better to push the work out for review a slice at a time rather than hanging onto it and sending a 100-patch set at the end. This patchset sits on top of my target-arm.next tree, which has the 'preliminary patchset' I sent out a while back in it. It includes: * implementation of PMSAv8 * banking of most of the main CPU registers which need it (the NVIC proper also gets banked exceptions, and the systick device is banked, but neither of those are done here) * the "let secure access the NS view of the NVIC" alias region * an implementation of the BXNS instruction, mostly as the simplest thing that needs the banking of stack pointers We don't yet actually properly swap the stack pointer around on other kinds of S<->NS transition including exception entry and exit. I have some patches working in that direction, so if the BXNS patch doesn't have enough context yet to make sense I can keep it around and resend it with those later. Next thing probably will be the NVIC changes, once I've got my head around the priority related changes v8M brings... Series available also at https://git.linaro.org/people/peter.maydell/qemu-arm.git v8m (on top of the target-arm.next stuff.) thanks -- PMM Peter Maydell (20): target/arm: Implement ARMv8M's PMSAv8 registers target/arm: Implement new PMSAv8 behaviour target/arm: Add state field, feature bit and migration for v8M secure state target/arm: Register second AddressSpace for secure v8M CPUs target/arm: Add MMU indexes for secure v8M target/arm: Make BASEPRI register banked for v8M target/arm: Make PRIMASK register banked for v8M target/arm: Make FAULTMASK register banked for v8M target/arm: Make CONTROL register banked for v8M nvic: Add NS alias SCS region target/arm: Make VTOR register banked for v8M target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M target/arm: Make MPU_RNR register banked for v8M target/arm: Make MPU_CTRL register banked for v8M target/arm: Make CCR register banked for v8M target/arm: Make MMFAR banked for v8M target/arm: Make CFSR register banked for v8M target/arm: Move regime_is_secure() to target/arm/internals.h target/arm: Implement BXNS, and banked stack pointers include/hw/intc/armv7m_nvic.h | 1 + target/arm/cpu.h | 100 ++++++++++++-- target/arm/helper.h | 2 + target/arm/internals.h | 26 ++++ target/arm/translate.h | 1 + hw/intc/armv7m_nvic.c | 294 +++++++++++++++++++++++++++++++++------ target/arm/cpu.c | 82 ++++++++--- target/arm/helper.c | 315 +++++++++++++++++++++++++++++++++--------- target/arm/machine.c | 104 ++++++++++++-- target/arm/translate.c | 52 ++++++- 10 files changed, 820 insertions(+), 157 deletions(-) -- 2.7.4