From patchwork Tue Sep 12 18:13:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112347 Delivered-To: patches@linaro.org Received: by 10.140.106.117 with SMTP id d108csp5548892qgf; Tue, 12 Sep 2017 11:13:41 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCnpGNKM+C3IVlJthspq90spf5dg71IDrk9ofGYbeCwgQPj88nuqj9WTtJZYIKnp5wkrIZH X-Received: by 10.28.214.212 with SMTP id n203mr331365wmg.10.1505240020904; Tue, 12 Sep 2017 11:13:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505240020; cv=none; d=google.com; s=arc-20160816; b=QS7GKv4DX7NtPhVsyRW3Bv+f++Ic4Oimg2ZfhUq40YN32g8ktIa9Rmr2efTH6JEX2B PEGzrosfUUUwxq6eSFHXx4Jpg0QbyKQnuk4el4OMPcXSYdmZnCaa0fv0tgFF8Mi0CZh+ 4qyIMO8wQJe0YqBDXWR0cRIiGpqQ9e4hPMJKva94TaESmsEB/I3iRdQF6zsaFjd3Vsed 7oxL8ksEoPR1kiJoe1UWyTxHKtnAnJA7DBo0IpTxQTMh56V9yx2tD8qG47aZntUlB91A gg0qsS/FmeR5L1bUzVOq4N9FED2pLMk5bytGAg2M3mvpsAOcKHiBx07tXU3SmubqUPt0 BBJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=message-id:date:subject:cc:to:from:arc-authentication-results; bh=zbso0yjuKiep3ESZFqiQIRKradVMLbiGGy80T+wTX6o=; b=JR0UzrXOofC4whySKpfqoBFMoqWbEuNpnGOPkWTfe99O+B7X3vFdKFXof86EXaSqtA NWc/xqwsE0QAriBUpKiUeiXfWJCkzp/RGsrx5Rujo31guSXzyGmyfEEAdPU6eJsmV0QV qBZORipywhGJIVe7vDzSuwowDbq7ad3xFPD297S11IYOEt4fG/xeSHxAK1mjO08NvY6C FpBEjqxaU8zxdCWOOk4qkUXpZvGA0l8kgouAwW/8Oxu2ElSA19FanuI1z6p/VNFZAR8J 8eCsBVl/CFnlvKDgKky123dqP5FE/Kb6vVwz5BJZaYGMLAo/2C6V9PsiROmA0txs2qLH ms/g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 30si9125168wrg.238.2017.09.12.11.13.40 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 11:13:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drpgp-00012m-JJ; Tue, 12 Sep 2017 19:13:39 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 00/19] ARMv8M: support security extn in the NVIC Date: Tue, 12 Sep 2017 19:13:47 +0100 Message-Id: <1505240046-11454-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 This patchset is another lump of v8M support. It mostly covers the NVIC, which has extensive changes to handle the fact that some exceptions are now banked. It sits on top of the set of minor fixes that I sent out the other day. (I have a chunk of patches that follow on from this to add the security extension support to exception entry and exit code, thus using the API changes made for the acknowledge and complete functions in the last patch. They need a little bit more baking, though, and 19 patches is enough as it is.) Testing status: I'm pretty happy that these patches are the right shape, but they might have minor bugs in the details. (My uvisor test case won't currently run very far because it wants the SG instruction.) They shouldn't break v7M code, though, and it seems better to me to move things into master and bugfix them later if necessary rather than hold onto an enormous stack of patches that's unreviewably large. thanks -- PMM Peter Maydell (19): target/arm: Implement MSR/MRS access to NS banked registers nvic: Add banked exception states nvic: Add cached vectpending_is_s_banked state nvic: Add cached vectpending_prio state nvic: Implement AIRCR changes for v8M nvic: Make ICSR.RETTOBASE handle banked exceptions nvic: Implement NVIC_ITNS registers nvic: Handle banked exceptions in nvic_recompute_state() nvic: Make set_pending and clear_pending take a secure parameter nvic: Make SHPR registers banked nvic: Compare group priority for escalation to HF nvic: In escalation to HardFault, support HF not being priority -1 nvic: Implement v8M changes to fixed priority exceptions nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear nvic: Handle v8M changes in nvic_exec_prio() target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index() nvic: Make ICSR banked for v8M nvic: Make SHCSR banked for v8M nvic: Support banked exceptions in acknowledge and complete include/hw/intc/armv7m_nvic.h | 33 +- target/arm/cpu.h | 62 ++- hw/intc/armv7m_nvic.c | 909 +++++++++++++++++++++++++++++++++++------- target/arm/cpu.c | 7 + target/arm/helper.c | 142 ++++++- hw/intc/trace-events | 13 +- 6 files changed, 996 insertions(+), 170 deletions(-) -- 2.7.4