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[PULL,00/31] target-arm queue

Message ID 1506012099-13605-1-git-send-email-peter.maydell@linaro.org
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Series target-arm queue | expand

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Peter Maydell Sept. 21, 2017, 4:41 p.m. UTC 
ARM queue: mostly patches from me, but also the Smartfusion2 board.

thanks
-- PMM

The following changes since commit 9ee660e7c138595224b65ddc1c5712549f0a278c:

  Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170921' into staging (2017-09-21 14:40:32 +0100)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170921

for you to fetch changes up to 6d262dcb7d108eda93813574c2061398084dc795:

  msf2: Add Emcraft's Smartfusion2 SOM kit (2017-09-21 16:36:56 +0100)

----------------------------------------------------------------
target-arm queue:
 * more preparatory work for v8M support
 * convert some omap devices away from old_mmio
 * remove out of date ARM ARM section references in comments
 * add the Smartfusion2 board

----------------------------------------------------------------
Peter Maydell (26):
      target/arm: Implement MSR/MRS access to NS banked registers
      nvic: Add banked exception states
      nvic: Add cached vectpending_is_s_banked state
      nvic: Add cached vectpending_prio state
      nvic: Implement AIRCR changes for v8M
      nvic: Make ICSR.RETTOBASE handle banked exceptions
      nvic: Implement NVIC_ITNS<n> registers
      nvic: Handle banked exceptions in nvic_recompute_state()
      nvic: Make set_pending and clear_pending take a secure parameter
      nvic: Make SHPR registers banked
      nvic: Compare group priority for escalation to HF
      nvic: In escalation to HardFault, support HF not being priority -1
      nvic: Implement v8M changes to fixed priority exceptions
      nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear
      nvic: Handle v8M changes in nvic_exec_prio()
      target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index()
      nvic: Make ICSR banked for v8M
      nvic: Make SHCSR banked for v8M
      nvic: Support banked exceptions in acknowledge and complete
      target/arm: Remove out of date ARM ARM section references in A64 decoder
      hw/arm/palm.c: Don't use old_mmio for static_ops
      hw/gpio/omap_gpio.c: Don't use old_mmio
      hw/timer/omap_synctimer.c: Don't use old_mmio
      hw/timer/omap_gptimer: Don't use old_mmio
      hw/i2c/omap_i2c.c: Don't use old_mmio
      hw/arm/omap2.c: Don't use old_mmio

Subbaraya Sundeep (5):
      msf2: Add Smartfusion2 System timer
      msf2: Microsemi Smartfusion2 System Register block
      msf2: Add Smartfusion2 SPI controller
      msf2: Add Smartfusion2 SoC
      msf2: Add Emcraft's Smartfusion2 SOM kit

 hw/arm/Makefile.objs            |   1 +
 hw/misc/Makefile.objs           |   1 +
 hw/ssi/Makefile.objs            |   1 +
 hw/timer/Makefile.objs          |   1 +
 include/hw/arm/msf2-soc.h       |  67 +++
 include/hw/intc/armv7m_nvic.h   |  33 +-
 include/hw/misc/msf2-sysreg.h   |  77 ++++
 include/hw/ssi/mss-spi.h        |  58 +++
 include/hw/timer/mss-timer.h    |  64 +++
 target/arm/cpu.h                |  62 ++-
 hw/arm/msf2-soc.c               | 238 +++++++++++
 hw/arm/msf2-som.c               | 105 +++++
 hw/arm/omap2.c                  |  49 ++-
 hw/arm/palm.c                   |  30 +-
 hw/gpio/omap_gpio.c             |  26 +-
 hw/i2c/omap_i2c.c               |  44 +-
 hw/intc/armv7m_nvic.c           | 913 ++++++++++++++++++++++++++++++++++------
 hw/misc/msf2-sysreg.c           | 160 +++++++
 hw/ssi/mss-spi.c                | 404 ++++++++++++++++++
 hw/timer/mss-timer.c            | 289 +++++++++++++
 hw/timer/omap_gptimer.c         |  49 ++-
 hw/timer/omap_synctimer.c       |  35 +-
 target/arm/cpu.c                |   7 +
 target/arm/helper.c             | 142 ++++++-
 target/arm/translate-a64.c      | 227 +++++-----
 default-configs/arm-softmmu.mak |   1 +
 hw/intc/trace-events            |  13 +-
 hw/misc/trace-events            |   5 +
 28 files changed, 2735 insertions(+), 367 deletions(-)
 create mode 100644 include/hw/arm/msf2-soc.h
 create mode 100644 include/hw/misc/msf2-sysreg.h
 create mode 100644 include/hw/ssi/mss-spi.h
 create mode 100644 include/hw/timer/mss-timer.h
 create mode 100644 hw/arm/msf2-soc.c
 create mode 100644 hw/arm/msf2-som.c
 create mode 100644 hw/misc/msf2-sysreg.c
 create mode 100644 hw/ssi/mss-spi.c
 create mode 100644 hw/timer/mss-timer.c

Comments

Peter Maydell Sept. 21, 2017, 5:28 p.m. UTC | #1 
On 21 September 2017 at 17:41, Peter Maydell <peter.maydell@linaro.org> wrote:
> ARM queue: mostly patches from me, but also the Smartfusion2 board.

>

> thanks

> -- PMM

>

> The following changes since commit 9ee660e7c138595224b65ddc1c5712549f0a278c:

>

>   Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170921' into staging (2017-09-21 14:40:32 +0100)

>

> are available in the git repository at:

>

>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170921

>

> for you to fetch changes up to 6d262dcb7d108eda93813574c2061398084dc795:

>

>   msf2: Add Emcraft's Smartfusion2 SOM kit (2017-09-21 16:36:56 +0100)

>

> ----------------------------------------------------------------

> target-arm queue:

>  * more preparatory work for v8M support

>  * convert some omap devices away from old_mmio

>  * remove out of date ARM ARM section references in comments

>  * add the Smartfusion2 board


Applied, thanks.

-- PMM