From patchwork Mon Oct 9 13:48:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 115237 Delivered-To: patches@linaro.org Received: by 10.80.163.170 with SMTP id s39csp2401618edb; Mon, 9 Oct 2017 06:48:43 -0700 (PDT) X-Google-Smtp-Source: AOwi7QD03hejPJbG6CKjGUeW9kBjklcANMOdBSvGuT0AujtrM4hHK6hbdF4aK2SN2i9P2QDFpfsN X-Received: by 10.223.199.130 with SMTP id l2mr10309031wrg.113.1507556923226; Mon, 09 Oct 2017 06:48:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507556923; cv=none; d=google.com; s=arc-20160816; b=WqTtTPKlKTxpDMw7vlDT6dQmcbrpx3dpfSmHso4YFBoqHkrw67zO9hcGeByz/57n5s HRrQHRjrJZPt/Gp5ib6kURTh6JtvFSIpxzwekg87gbafqlBn5gc92qAdQbeKt+OLKLsf +Klql347iL5O9rrtQO0YT3Kyf+3QGQA0x7FSLly0QL72cT2RXpKtBsOOyMgA8DRRw6mq bJ+gi4Zp3BfLVcggIRqUOMqoQcqLD++caILVF2nQMtsoe0kIaQGX1GYGt2rSEIR+HtIs cZlKNwbVBMJ1VPTo+gm+9VcOKc9dZl3/OcmpdYDKdO3D7s9+K9dml1C9nO9Jct/PmVNS shoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=6vqjyy9nKnaLOAAgZuo51kq89B06fjP7ezWbzc6dKq0=; b=S3tHybXqBmqU93u2rqPvPIZEjnKL93rdK3jYKN+47L38AWcsUgOQkPpA8pugEmKbf1 MSluyz0TagUsPgtIrh8VpfWnDGJyNZoQ4cDg9Ub+N/lHIh6abU0BQ3e9yIy2wyPbD2hQ ep9KeT+Il5W/qqBW0V6ShiVXqGFBbBPisGOjtqQ7Zm2XGuTZXrEQ89PBHWqBb090YSk0 EhVKoP9UiDNC6otOpp848jzbE+9r6wYHVt2Pn7l4fx9511ANWLcCbf/bq/AO8ma1FjQU aMzmfndC48vzvs20Sqp7sYWgy0omJvZbb9F7IC4XjXyQqrl+UPKDi04PXPXdG3L1g/u6 sMVg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id f78si6781239wmh.125.2017.10.09.06.48.43 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 06:48:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1e1YQA-0004WH-7w; Mon, 09 Oct 2017 14:48:38 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson , patches@linaro.org Subject: [PATCH 0/9] v8M: BLXNS, SG, secure function return Date: Mon, 9 Oct 2017 14:48:30 +0100 Message-Id: <1507556919-24992-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 This patchset is mostly implementation of SG, BLXNS and secure function return. Parts of it were in the previous patchset, but had a bug which I've fixed in the SG implementation where we read the first half of the insn twice by mistake. Patch 1 is a new trivial bugfix. Patches 2-4 were in the previous set; only 2 has changed. Patches 5-8 perform some refactoring so that we can correctly implement the behaviour of a handful of Thumb instructions which must be unconditional even when they appear inside an IT block: SG, HLT and BKPT. Patch 9 implements the final edge cases of the SG insn. The refactoring has the nice property that we don't have to pass the CPU env pointer into the bulk of the thumb decode functions any more. I suspect it also might fix bugs in setting breakpoints on instructions inside IT blocks, though we haven't had any complaints about that so perhaps gdb works around it by setting breakpoints on both the cc pass and cc fail next instructions in an IT block... Peter Maydell (9): target/arm: Add M profile secure MMU index values to get_a32_user_mem_index() target/arm: Implement SG instruction target/arm: Implement BLXNS target/arm: Implement secure function return target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1 target/arm: Pull Thumb insn word loads up to top level target-arm: Simplify insn_crosses_page() target/arm: Support some Thumb insns being always unconditional target/arm: Implement SG instruction corner cases target/arm/helper.h | 1 + target/arm/internals.h | 8 ++ target/arm/helper.c | 306 +++++++++++++++++++++++++++++++++++++++++++++--- target/arm/translate.c | 310 +++++++++++++++++++++++++++++++++---------------- 4 files changed, 515 insertions(+), 110 deletions(-) -- 2.7.4