From patchwork Thu Mar 1 11:23:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 130135 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp2673380edc; Thu, 1 Mar 2018 03:24:35 -0800 (PST) X-Google-Smtp-Source: AG47ELvkvY45oWf+zlrUFycuFIDG0LeH2/JNE32Cb9IL7YuJ/6Ckm8mrj2svfe1BgOzs7amMtkxh X-Received: by 2002:a25:888e:: with SMTP id d14-v6mr809161ybl.163.1519903475756; Thu, 01 Mar 2018 03:24:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519903475; cv=none; d=google.com; s=arc-20160816; b=kE7kf8CT80GG6wq0RCCfoGYGQrk9GWlBquA53wrQWx/4uNZwXCULFlQyq7FASnBMka 0jPQ2eoD0KRHLl+4EFOAAPBMoJpMe8pjjhXsYixt28e593ff1bVC5oxFKg+VdmJxhF1u qNuLl4o51tk/ERCezh+or53ba+KKvFFC9thwiyOkkYqBuN317LRDFnwE/ur0ixrWpHfT gTZiuINqMpz0NE/6xXkAExOh1YRLAIVL0ZY2ZDDBHZ1fB0wKZQ4c6W+paNA5vnH/lWF9 m/s1zeaJ7loAETSYBe5aiGjZjcNXzYfYSI/PDmg5hSvIgxga2keuG3qgXJDuFFwBafUN mWyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:message-id:date:to:from :arc-authentication-results; bh=5YlllYd6uakU5JpCTUQjhA2sLfEnQbMUKyJgczN+ORw=; b=q6K3N6hIcC1qasijEkYYlOlsb4a9DBR0JS2alYR1DT25T8UXE0KPrdQ/wI3S/woH12 8preH+m+k3Q9VzznMJ74ymrWsihjcKTPlvaHEaTXFJ+CwzBVra/LhiUrLpvGrDHGu6cu TEnhmmeukCQRqwSzuvPVR0vnoHrIG7rpzoZD/pNVaSARkzX+Y0N1G+7MPWv8BdQj2Tb3 gEHTNE2lg+D0GBBSJ3FUq9ESl+Nkd98KXjmp2j7QgSVOESY4lZGBIdwEuzKO8T5B+Nvc arUo8gN+aVNKHYxP7GdLjV1OwQzaztjQUtWTnvmxTepggEv5cJZUOMmKR+1raD7VAUow Jwhw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id f131si612992ywb.49.2018.03.01.03.24.35 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 01 Mar 2018 03:24:35 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55704 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMKB-0003g5-4Q for patch@linaro.org; Thu, 01 Mar 2018 06:24:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33636) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMJp-0003fd-RA for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1erMJo-00084N-KF for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:13 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46698) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1erMJo-00082m-AT for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:12 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1erMJg-0000X7-Hc for qemu-devel@nongnu.org; Thu, 01 Mar 2018 11:24:04 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Mar 2018 11:23:21 +0000 Message-Id: <20180301112403.12487-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 00/42] target-arm queue X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Arm queue -- I have more stuff pending but I prefer to push this first lot out and keep the pull below 50 patches. Most of this is Alex's FP16 support work. -- PMM The following changes since commit 6697439794f72b3501ee16bb95d16854f9981421: Merge remote-tracking branch 'remotes/kraxel/tags/usb-20180227-pull-request' into staging (2018-02-27 17:50:46 +0000) are available in the Git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180301 for you to fetch changes up to c22e580c2ad1cccef582e1490e732f254d4ac064: MAINTAINERS: Update my email address (2018-03-01 11:13:59 +0000) ---------------------------------------------------------------- target-arm queue: * update MAINTAINERS for Alistair's new email address * add Arm v8.2 FP16 arithmetic extension for linux-user * implement display connector emulation for vexpress board * xilinx_spips: Enable only two slaves when reading/writing with stripe * xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands * hw: register: Run post_write hook on reset ---------------------------------------------------------------- Alex Bennée (31): include/exec/helper-head.h: support f16 in helper calls target/arm/cpu64: introduce ARM_V8_FP16 feature bit target/arm/cpu.h: update comment for half-precision values target/arm/cpu.h: add additional float_status flags target/arm/helper: pass explicit fpst to set_rmode arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) arm/translate-a64: handle_3same_64 comment fix arm/translate-a64: initial decode for simd_three_reg_same_fp16 arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16 arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16 arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16 arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16 arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed arm/translate-a64: add FP16 x2 ops for simd_indexed arm/translate-a64: initial decode for simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 arm/helper.c: re-factor recpe and add recepe_f16 arm/translate-a64: add FP16 FRECPE arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16 arm/helper.c: re-factor rsqrte and add rsqrte_f16 arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FMOV to simd_mod_imm arm/translate-a64: add all FP16 ops in simd_scalar_pairwise arm/translate-a64: implement simd_scalar_three_reg_same_fp16 arm/translate-a64: add all single op FP16 to handle_fp_1src_half Alistair Francis (2): hw: register: Run post_write hook on reset MAINTAINERS: Update my email address Corey Minyard (2): i2c: Fix some brace style issues i2c: Move the bus class to i2c.h Francisco Iglesias (2): xilinx_spips: Enable only two slaves when reading/writing with stripe xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands Linus Walleij (3): hw/i2c-ddc: Do not fail writes hw/sii9022: Add support for Silicon Image SII9022 arm/vexpress: Add proper display connector emulation Peter Maydell (2): target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU linux-user: Report AArch64 FP16 support via hwcap bits hw/display/Makefile.objs | 1 + include/exec/helper-head.h | 3 + include/fpu/softfloat.h | 18 +- include/hw/i2c/i2c.h | 23 +- include/hw/register.h | 6 +- target/arm/cpu.h | 34 +- target/arm/helper-a64.h | 33 + target/arm/helper.h | 14 +- hw/arm/vexpress.c | 6 +- hw/core/register.c | 8 + hw/display/sii9022.c | 191 ++++++ hw/i2c/core.c | 18 - hw/i2c/i2c-ddc.c | 4 +- hw/ssi/xilinx_spips.c | 43 +- linux-user/elfload.c | 2 + target/arm/cpu64.c | 1 + target/arm/helper-a64.c | 269 +++++++++ target/arm/helper.c | 481 ++++++++------- target/arm/translate-a64.c | 1266 +++++++++++++++++++++++++++++++++------ target/arm/translate.c | 12 +- MAINTAINERS | 12 +- default-configs/arm-softmmu.mak | 2 + hw/display/trace-events | 5 + 23 files changed, 1981 insertions(+), 471 deletions(-) create mode 100644 hw/display/sii9022.c