From patchwork Tue Mar 6 12:55:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 130786 Delivered-To: patches@linaro.org Received: by 10.46.66.2 with SMTP id p2csp3903070lja; Tue, 6 Mar 2018 04:55:29 -0800 (PST) X-Google-Smtp-Source: AG47ELvnxwLEQz7oWYRwmc/tXIUeV1dAE/fN5QWQF4aAdeLBwFpbG8LpDdC0ahlNgZ7xXCxcHnrg X-Received: by 10.28.4.216 with SMTP id 207mr8324149wme.108.1520340929449; Tue, 06 Mar 2018 04:55:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520340929; cv=none; d=google.com; s=arc-20160816; b=LsdVEqfXQqQ99mtsMH/lCe6vJ8PC8Zv67FstWO/q6vb43L1dvYvRviBXzJsIElPPBQ /cffT5gRpTv5PL7wdHjsE5IJyKw1FtJj0eOTLGKd4K2PW4JFOpLYtuS/7dv6izndlO33 K7c+kweGoezUdyJF074jgiYMCv/FP6jAA0Pcz8bYt8AUsOqQEMSm9oFJmIu3TAdnVYAa Q1EcopRMyt44s3w/VP8VDBdoZWIrpLNSPD2vTo6vAElkuHjddR44GySNj9Wdz+FbIAzs LumjvfGb/eoG/vbkKVIaGQ4M2T1g24Ibcgw7oTrJNLZl6e0QcOoNtElIqWt9GwyPUTVI buHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=IeNAqk3slAvK6FMBH0uSSjOyZsXpZO9fZ+tCrT4NtZk=; b=sgKwC6hu8fJVvplJyEoa65HFvAk9SacWATOoK765xqnRLlVihD83BXj+hEGCeX1RYE YQP4uhqih/fzKRnC6KCSCNRRs9Ts/Vp9TxFvoJDIyNT3w+15QpNcGzr98wy1C+i05vNo Fq4E3DCsQVxFwup44QhSdxCNezX2w9HvZ4kTfSV//ZuhyYOFYdNquIAgOSXimHCTEcTB aUt8QpqXLlHbUd1lijL0H3qaSrTthsWKL86lGbBivaxY/rscjwGIEUwMlDfGEaOaIEtX P5r6Dau4DQ5RLLuzgqgZu5Qr1ZGE1mu+RBcg8BneDbfUHJBxu9MF4Aicp/bMfLoKtir1 +h4Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 131si468786wmt.225.2018.03.06.04.55.29 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Mar 2018 04:55:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1etC7r-0004VA-KF; Tue, 06 Mar 2018 12:55:27 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Igor Mammedov , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= Subject: [PATCH v2 0/6] arm: support -cpu max (and gic-version=max) Date: Tue, 6 Mar 2018 12:55:20 +0000 Message-Id: <20180306125526.27838-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 MIME-Version: 1.0 This patchset adds support for '-cpu max' to Arm, along the lines of the existing support we have for x86 targets: * under KVM, -cpu max is the same as -cpu host * under TCG, -cpu max means "emulate with as many features as possible" -cpu max is supported for both usermode and system emulation, again following the x86 line. NB that cross-QEMU-version migration is not supported for -cpu max: in future the definition of "maximum set of features" will change as we add more emulation features. The patchset also adds support to the virt board for the "max" option to -machine gic-version, requesting "best available interrupt controller", with the same semantics as -cpu max. Together these should assist users like libguestfs that just want to be able to run code without having to figure out what the right command line arguments for this particular host system are. The patches make 'any' a synonym for 'max', using the approach of putting a compat hack into arm_cpu_class_by_name() that Igor suggested. For the moment, we don't enable any of the CPU feature bits in 'max' that aren't in the a15/a57 if we're doing system emulation mode. This is a combination of: * some of those bits are currently only implemented sufficiently for user-only mode, not for system emulation * we would also need to update ID register bits to advertise the extra features We should certainly do that, but I'd like to get basic -cpu max support into 2.12, and the softfreeze deadline is rapidly approaching, so I've opted to postpone that to post 2.12. If people have the time to review this series this week I'd really appreciate it. Changes since v1: * the "check CPU realize succeeded in virt board" patch is in master * the "target/arm: Make 'any' CPU just an alias for 'max'" is new, and unifies 'any' with 'max' as suggested in review of v1 * the other patches are essentially unchanged thanks -- PMM Peter Maydell (6): target/arm: Query host CPU features on-demand at instance init target/arm: Move definition of 'host' cpu type into cpu.c target/arm: Add "-cpu max" support target/arm: Make 'any' CPU just an alias for 'max' hw/arm/virt: Add "max" to the list of CPU types "virt" supports hw/arm/virt: Support -machine gic-version=max target/arm/cpu-qom.h | 2 ++ target/arm/cpu.h | 5 +++ target/arm/kvm_arm.h | 35 +++++++++++++------ hw/arm/virt.c | 30 +++++++++++------ target/arm/cpu.c | 95 +++++++++++++++++++++++++++++++++++++++++++--------- target/arm/cpu64.c | 66 +++++++++++++++++++++++------------- target/arm/kvm.c | 53 ++++++++++------------------- target/arm/kvm32.c | 8 ++--- target/arm/kvm64.c | 8 ++--- 9 files changed, 198 insertions(+), 104 deletions(-) -- 2.16.2