From patchwork Thu Aug 2 17:40:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 143366 Delivered-To: patches@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2441677ljj; Thu, 2 Aug 2018 10:40:46 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdVzqSqIWfjofdPrslyIGn7i1G+0GsTIfG7PzCrKLDHxJeUAZVDG9fhPB8MtgKe5lHbliQ+ X-Received: by 2002:adf:f74d:: with SMTP id z13-v6mr304160wrp.85.1533231646361; Thu, 02 Aug 2018 10:40:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533231646; cv=none; d=google.com; s=arc-20160816; b=cmtiwBvHv3wZsQRoByyHFdq72QT97mcTGf+BsurgkVvou+7Is/KZWVYiqlB8KOCKE7 mSw/1Jziz3NuJbCKdrAosGQnmiv057O/qAK2oVrrZM1ZHhcyBeqmo6GCrBHyhsGL9gIp 8eh6/7bQuafAmx2GTgfjw4G1/8rL3O5D9ejg6ykc4QXeEPX/HJxyRgupYRO7vpSsXAQI TiTCkVEOXjqSnKxykxrj7zwPIyPeHp9ewPNX+7TgAd15Wp38eVMDvuNpMS516F7IrNpR wB7BOGj1qJYtuv6CFAL00Tvs8Gl111akv8qIlqvwuwMh36tQsMzxVQZn3oYSDvYXIGoX WuOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=message-id:date:subject:cc:to:from:arc-authentication-results; bh=NKs1Wdqo3Fz4F2D5CduZe7N+foLJdrSL3YY4LDAmOz8=; b=qtwPVd8NvaMk5i2ao4/h7oqHyQtaFaFQOuV7Ypx2uXMg/a/PYRUleTH4Q9XFCFxOU9 dJgDmH6BHCDQcfJqbdE2wpJQkFSDagLujV1myLT4+3gF8Gndp4xvMO94iaXkT7pNH6n6 G1ojoFLFV1V1F4Ebx3I8CG52yAE2nZcp6dnbIU6NTq/2BF3J31CvBck8g2gjRjCZdI0V sc9mU5nL7hJ6fUQkFYT7NJaT4IFJttCIVoOKDW0rxsCA7NJIpNPnkKtjsvewy7zg4DkI 1U6RyE9gHFpD1oMukEE7Ka7Cxmsfevb/UW105piAAtarFpq1AgUS73Orvdvt6UPGROuW pgoA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 65-v6si1787609wmj.182.2018.08.02.10.40.46 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 02 Aug 2018 10:40:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1flHae-0006Tb-Ph; Thu, 02 Aug 2018 18:40:44 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Jason Wang Subject: [PATCH 0/2] hw/net/pcnet-pci: Convert away from old_mmio accessors Date: Thu, 2 Aug 2018 18:40:40 +0100 Message-Id: <20180802174042.29234-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 This patchset converts the pcnet-pci's MMIO BAR MemoryRegionOps away from the old_mmio accessors. It does it in two stages: * patch 1 is a no-behaviour-change patch which replaces the old split byte/word/long accessor functions with single read and write functions which take the size, and look suspiciously similar but not identical to the existing pcnet_ioport_read/write functions * patch 2 then drops the new read and write functions and just uses the ioport read/write functions My reason for structuring it like this is that I'm pretty sure that the discrepancy between the MMIO BAR accessors and the IO BAR accessors is just a bug (one which we fixed for the IO BAR accessors in commit 7ba79741970 in 2011). But if I'm wrong I want us to be able to revert the behaviour change easily without that bringing back a use of the old_mmio accessors (which might not even compile if we need to revert after we've finally managed to drop those entirely). The bug as fixed in patch 2 is that for the MMIO BAR we were not honouring the DWIO bit (which indicates whether the device is in 16-bit or 32-bit IO mode) when doing accesses to the aprom range 0x0..0xf. We were already honouring DWIO for accesses to the 0x10..0x1f range, and my trawling through datasheets indicates that DWIO applies identically to MMIO and IO BARs (see patch 2's commit message for details and references). This is awkwardly hard to test, though, because Linux's pcnet driver only uses port IO as far as I can tell. (Likely this is why the bug has remained unnoticed for so long.) thanks -- PMM Peter Maydell (2): hw/net/pcnet-pci: Convert away from old_mmio accessors hw/net/pcnet-pci: Unify pcnet_ioport_read/write and pcnet_mmio_read/write hw/net/pcnet-pci.c | 98 +++------------------------------------------ hw/net/trace-events | 6 --- 2 files changed, 6 insertions(+), 98 deletions(-) -- 2.17.1 Reviewed-by: Richard Henderson