From patchwork Tue Oct 2 16:35:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 147997 Delivered-To: patches@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp5372061lji; Tue, 2 Oct 2018 09:36:00 -0700 (PDT) X-Google-Smtp-Source: ACcGV60KCUTl8lLj+5oxYSWMbwO6dmJ2SKLfTgqlTF9M51kNMUkYvZKY9Lzt6tDzdR7L2BF19WoN X-Received: by 2002:a5d:4208:: with SMTP id n8-v6mr9445080wrq.260.1538498160156; Tue, 02 Oct 2018 09:36:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538498160; cv=none; d=google.com; s=arc-20160816; b=TA79N6IJnHUEraxpf9B+DeoG3CKCqKQl8a+YIyalyBmGrODZaNI253W8/ck2/1UDVG uSu/GB74TvUG8AoGzIBpLGb/I7yLrrOf4AEp5BM3hU43uEosDVnSkWQWars42Zc1+/ZW UZeZKqoEaiPMEU2BWPfiLc8uuXm3Jrkt6K8V8BGvrAp59COUqU5T9mVg4ZOQEmCLwYGm yg7maB7q58Fs1erWXAtA8mpAih4PbQvXX48xcixP3i6M7kTw8LmDOU9eKQaqsZPzC2el D1xl5YvR1kkhv0G/27LfN2FGwtuJob0kNfE5hHHAe6+c71pTqYwuECBH640kVTlhLuXl wcIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from; bh=5SPPZPQlCE4vnTEmLDUArQeO34NcBkogPdKxUojbBi0=; b=GxvCy691+XCd2/Aw6NRRiAskijKEPppPiFnqHHF7rV/+Ap3e18aBm5q2/MT8ejWcAC B2cA8fPYlsnTjeeJUq1g4+WyCN7sJ4q2j+RrNBfIJvY6lgAv8F7P+gA1mPyCgJFffZo/ JlzTTESQP5nuxehsu2pznZqUeHtH2FsxknPIA7dl9FPdwyXveDqHcpDZXwjm4EONjMKb W+Hmrr/mCYQKfikQe/XFyLz/c5cs9ZmC7yqrdFFcnGWaDsHyD+W1L/d4v0wiDCE5S1qm OQgJq6aCVDz5FCtg0siqlBFTKYnhwRugwdnluB5uBYfH5o8l++6a1lH2nwPfbHpPb42P 9V0w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id m17-v6si10498682wrr.58.2018.10.02.09.35.59 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 02 Oct 2018 09:36:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1g7NeR-0007GF-1S; Tue, 02 Oct 2018 17:35:59 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 00/13] target/arm: Implement v8M stack limit checks Date: Tue, 2 Oct 2018 17:35:43 +0100 Message-Id: <20181002163556.10279-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 MIME-Version: 1.0 This patchset implements the v8M stack limit checking feature, which is the last missing piece of the v8M architectural support. Note that the stack limit triggers when the SP value is changed to something below the limit, not when a load or store is performed below the limit. It's also done only for certain instructions that update SP, not for every possible way to change SP. For loads and stores which do writeback to SP there are also some rules about what parts of the load/store are permitted to happen if the check triggers -- we keep things simple by taking the approach of doing the check first so that no accesses are done. We take a straightforward approach to implementing the checks: generating a call to a helper function which does the comparison and might raise an exception. This obviously imposes some overhead for the common case where the limit isn't being breached, but generating code for a compare-and-conditionally-call seemed too tricky to insert into the existing code... thanks -- PMM Peter Maydell (13): target/arm: Define new TBFLAG for v8M stack checking target/arm: Define new EXCP type for v8M stack overflows target/arm: Move v7m_using_psp() to internals.h target/arm: Add v8M stack checks on ADD/SUB/MOV of SP target/arm: Add some comments in Thumb decode target/arm: Add v8M stack checks on exception entry target/arm: Add v8M stack limit checks on NS function calls target/arm: Add v8M stack checks for LDRD/STRD (imm) target/arm: Add v8M stack checks for Thumb2 LDM/STM target/arm: Add v8M stack checks for T32 load/store single target/arm: Add v8M stack checks for Thumb push/pop target/arm: Add v8M stack checks for VLDM/VSTM target/arm: Add v8M stack checks for MSR to SP_NS target/arm/cpu.h | 9 ++ target/arm/helper.h | 2 + target/arm/internals.h | 38 ++++++++ target/arm/translate.h | 1 + target/arm/helper.c | 99 ++++++++++++++++----- target/arm/op_helper.c | 23 ++++- target/arm/translate.c | 198 +++++++++++++++++++++++++++++++++++++---- 7 files changed, 330 insertions(+), 40 deletions(-) -- 2.19.0