[v2,00/27] target/arm: Implement ARMv8.3-PAuth

Message ID	20181214052410.11863-1-richard.henderson@linaro.org
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 23:23:43 -0600 Message-Id: <20181214052410.11863-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH v2 00/27] target/arm: Implement ARMv8.3-PAuth Precedence: list Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/arm: Implement ARMv8.3-PAuth \| expand [v2,00/27] target/arm: Implement ARMv8.3-PAuth [v2,01/27] target/arm: Add state for the ARMv8.3-PAuth extension [v2,02/27] target/arm: Add SCTLR bits through ARMv8.5 [v2,03/27] target/arm: Add PAuth active bit to tbflags [v2,04/27] target/arm: Add PAuth helpers [v2,05/27] target/arm: Decode PAuth within system hint space [v2,06/27] target/arm: Rearrange decode in disas_data_proc_1src [v2,07/27] target/arm: Decode PAuth within disas_data_proc_1src [v2,08/27] target/arm: Decode PAuth within disas_data_proc_2src [v2,09/27] target/arm: Move helper_exception_return to helper-a64.c [v2,10/27] target/arm: Add new_pc argument to helper_exception_return [v2,11/27] target/arm: Rearrange decode in disas_uncond_b_reg [v2,12/27] target/arm: Decode PAuth within disas_uncond_b_reg [v2,13/27] target/arm: Decode Load/store register (pac) [v2,14/27] target/arm: Move cpu_mmu_index out of line [v2,15/27] target/arm: Introduce arm_mmu_idx [v2,16/27] target/arm: Introduce arm_stage1_mmu_idx [v2,17/27] target/arm: Create ARMVAParameters and helpers [v2,18/27] target/arm: Reuse aa64_va_parameters for setting tbflags [v2,19/27] target/arm: Export aa64_va_parameters to internals.h [v2,20/27] target/arm: Implement pauth_strip [v2,21/27] target/arm: Implement pauth_auth [v2,22/27] target/arm: Implement pauth_addpac [v2,23/27] target/arm: Implement pauth_computepac [v2,24/27] target/arm: Add PAuth system registers [v2,25/27] target/arm: Enable PAuth for -cpu max [v2,26/27] target/arm: Enable PAuth for user-only, part 2 [v2,27/27] target/arm: Tidy TBI handling in gen_a64_set_pc

Message ID

20181214052410.11863-1-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Thu, 13 Dec 2018 23:23:43 -0600
Message-Id: <20181214052410.11863-1-richard.henderson@linaro.org>
Subject: [Qemu-devel] [PATCH v2 00/27] target/arm: Implement ARMv8.3-PAuth
Precedence: list
Cc: peter.maydell@linaro.org
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>

Series

target/arm: Implement ARMv8.3-PAuth | expand

Message

Richard Henderson Dec. 14, 2018, 5:23 a.m. UTC

Lots of little changes since v1, but many of which are noted
within each patch.  This version works in system mode, using

https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/log/?h=for-next/core


r~

Richard Henderson (27):
  target/arm: Add state for the ARMv8.3-PAuth extension
  target/arm: Add SCTLR bits through ARMv8.5
  target/arm: Add PAuth active bit to tbflags
  target/arm: Add PAuth helpers
  target/arm: Decode PAuth within system hint space
  target/arm: Rearrange decode in disas_data_proc_1src
  target/arm: Decode PAuth within disas_data_proc_1src
  target/arm: Decode PAuth within disas_data_proc_2src
  target/arm: Move helper_exception_return to helper-a64.c
  target/arm: Add new_pc argument to helper_exception_return
  target/arm: Rearrange decode in disas_uncond_b_reg
  target/arm: Decode PAuth within disas_uncond_b_reg
  target/arm: Decode Load/store register (pac)
  target/arm: Move cpu_mmu_index out of line
  target/arm: Introduce arm_mmu_idx
  target/arm: Introduce arm_stage1_mmu_idx
  target/arm: Create ARMVAParameters and helpers
  target/arm: Reuse aa64_va_parameters for setting tbflags
  target/arm: Export aa64_va_parameters to internals.h
  target/arm: Implement pauth_strip
  target/arm: Implement pauth_auth
  target/arm: Implement pauth_addpac
  target/arm: Implement pauth_computepac
  target/arm: Add PAuth system registers
  target/arm: Enable PAuth for -cpu max
  target/arm: Enable PAuth for user-only, part 2
  target/arm: Tidy TBI handling in gen_a64_set_pc

 target/arm/cpu.h           | 171 +++++-----
 target/arm/helper-a64.h    |  14 +
 target/arm/helper.h        |   1 -
 target/arm/internals.h     |  62 ++++
 target/arm/translate.h     |   2 +
 target/arm/cpu.c           |   6 +
 target/arm/cpu64.c         |   4 +
 target/arm/helper-a64.c    | 629 +++++++++++++++++++++++++++++++++++++
 target/arm/helper.c        | 500 ++++++++++++++++++-----------
 target/arm/op_helper.c     | 155 ---------
 target/arm/translate-a64.c | 534 ++++++++++++++++++++++++++-----
 11 files changed, 1581 insertions(+), 497 deletions(-)

-- 
2.17.2