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[209.51.188.17]) by mx.google.com with ESMTPS id m1si92935261wrb.215.2019.01.28.14.55.32 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 28 Jan 2019 14:55:32 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=anZp+7zs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:39740 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFoR-0006qf-QG for patch@linaro.org; Mon, 28 Jan 2019 17:55:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47287) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goFcG-0006zi-CZ for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:42:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goFRA-0006AM-VQ for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:30 -0500 Received: from mail-ot1-x32b.google.com ([2607:f8b0:4864:20::32b]:44587) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goFR9-000693-8O for qemu-devel@nongnu.org; Mon, 28 Jan 2019 17:31:27 -0500 Received: by mail-ot1-x32b.google.com with SMTP id g16so12158035otg.11 for ; Mon, 28 Jan 2019 14:31:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=jwZhT3c+3RTTqwpJxB/XpwYvY6bjEqf1jZksEHvXI3M=; b=anZp+7zsWKsKtBwq7Uf6bUCNwAMEF3hGwo3UDRbmME4p8X2PW454fNLGzkjQ4Rc4R8 UhP/2nj3Ty2u104df/EBR0Gn+BH1TP5Yqj+rResHuVBiTB2moIAJ+gLb2giNipaYU61+ C8380kZhExgK8Mc9hruUERRy6gcQfMxyomEYU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=jwZhT3c+3RTTqwpJxB/XpwYvY6bjEqf1jZksEHvXI3M=; b=CD9DJ/PIcmTziAFygs70v/WLoRv1+BizuIS8gVnoqkW+tfPkddEQSkE+glvg3vytqp GVsG51VdoV+dOgoes+9Auf8Pk3elgcTdvyYyuMjEdQtd+uGJH/usD20z8jr+3BpOFIoz P+zpFAC6bsRUzXUQ1LY2j2aGdPy8O8Z9BPJuv78CrP3smL61U++g3BKhp6HsKMbsEHG0 e8lu+1tnxTtSDzqwUvQG8D9LHYU4NxdgDOS2vmTOTHkLH2iLXnSuFDKXf0BRE6tJEpkV 74Fk5llv2Kxr1pTAOV2hyhzQISCsNDjB2fIcxxB4PaHLlKJ+HRkpVgfu815oTZhlqkNV VejQ== X-Gm-Message-State: AJcUukcTYus0sat2qhTwIGOz2MatGjhHo9/ZF1/Y5k5xG5yt9cR16oRD rclNctodrx1VUM8+YUHJg/4NAfMku4o= X-Received: by 2002:a9d:a2e:: with SMTP id 43mr16448599otg.8.1548714684991; Mon, 28 Jan 2019 14:31:24 -0800 (PST) Received: from cloudburst.twiddle.net ([12.227.73.85]) by smtp.gmail.com with ESMTPSA id v3sm7460438oib.57.2019.01.28.14.31.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 14:31:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 14:31:06 -0800 Message-Id: <20190128223118.5255-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::32b Subject: [Qemu-devel] [PATCH v2 00/12] target/arm: Implement ARMv8.5-BTI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The branch target identification extension does not yet have kernel or gcc support. It should be in shape for developing those though. In system mode I do honor the GP bit from the page tables. In user-only mode, there is a way to pretend that the GP bit is always set. Further linux-user changes will have to track the ABI that gets developed. In the meantime, provide a statically linable make check-tcg test for the functionality. Changes since v2: * Rebase on master. * Incorporate feedback from Peter. r~ Richard Henderson (12): target/arm: Introduce isar_feature_aa64_bti target/arm: Add PSTATE.BTYPE target/arm: Add BT and BTYPE to tb->flags exec: Add target-specific tlb bits to MemTxAttrs target/arm: Cache the GP bit for a page in MemTxAttrs target/arm: Default handling of BTYPE during translation target/arm: Reset btype for direct branches target/arm: Set btype for indirect branches target/arm: Add x-guarded-pages cpu property for user-only target/arm: Enable BTI for -cpu max linux-user/aarch64: Reset btype for syscalls and signals tests/tcg/aarch64: Add bti smoke test include/exec/memattrs.h | 10 ++ target/arm/cpu.h | 24 +++- target/arm/internals.h | 6 + target/arm/translate.h | 9 ++ linux-user/aarch64/cpu_loop.c | 15 +++ target/arm/cpu64.c | 22 ++++ target/arm/helper.c | 28 +++-- target/arm/translate-a64.c | 193 +++++++++++++++++++++++++++++- tests/tcg/aarch64/bti-1.c | 61 ++++++++++ tests/tcg/aarch64/bti-crt.inc.c | 51 ++++++++ tests/tcg/aarch64/Makefile.target | 7 +- 11 files changed, 415 insertions(+), 11 deletions(-) create mode 100644 tests/tcg/aarch64/bti-1.c create mode 100644 tests/tcg/aarch64/bti-crt.inc.c -- 2.17.2