mbox series

[for-4.1,00/35] tcg: Move the softmmu tlb to CPUNegativeOffsetState

Message ID 20190323190925.21324-1-richard.henderson@linaro.org
Headers show
Series tcg: Move the softmmu tlb to CPUNegativeOffsetState | expand

Message

Richard Henderson March 23, 2019, 7:08 p.m. UTC
This started merely as an attempt to reduce the size of each
softmmu lookup by using smaller offsets from env.  But in the
end it also represents a significant cleanup in the boilerplate
that each target must define.

With respect to the initial goal, here are the relevant code
snips generated for loading the mask & table fields for a
qemu_ld from an aarch64 guest on the indicated host.

BEFORE:

x86_64:
0x7f9698c5f73b:  48 23 bd 98 32 00 00     andq     0x3298(%rbp), %rdi
0x7f9698c5f742:  48 03 bd d8 32 00 00     addq     0x32d8(%rbp), %rdi

aarch64:
0xffff9e001e28:  91400e61  add      x1, x19, #3, lsl #12
0xffff9e001e2c:  f9414c20  ldr      x0, [x1, #0x298]
0xffff9e001e30:  f9416c21  ldr      x1, [x1, #0x2d8]

aarch32:
0xa2b7f0d4:  e2862a03  add      r2, r6, #0x3000
0xa2b7f0d8:  e592c20c  ldr      ip, [r2, #0x20c]
0xa2b7f0dc:  e592222c  ldr      r2, [r2, #0x22c]

AFTER:

x86_64:
0x7fa40a000154:  48 23 7d e0              andq     -0x20(%rbp), %rdi
0x7fa40a000158:  48 03 7d e8              addq     -0x18(%rbp), %rdi

aarch64:
0xffffa20001b4:  a97e0660  ldp      x0, x1, [x19, #-0x20]

aarch32:
0xa2c7f0d4:  e14604d8  ldrd     r0, r1, [r6, #-0x48]

The other tcg hosts do not see as significant difference.  PPC and
mips have 16-bit signed offsets, and have no load-pair/multiple.
S390x has 20-bit signed offsets and, like x86, uses a read-operate
instruction form.  Sparc and RISC-V have 13 and 12-bit signed offsets
respectively, and so do avoid an extra add insn in this case, but
do not have load-pair/multiple.

All that said, in the end I'm most happy with the diffstat result.


r~


Richard Henderson (35):
  tcg: Fold CPUTLBWindow into CPUTLBDesc
  tcg: Split out target/arch/cpu-param.h
  tcg: Create struct CPUTLB
  cpu: Define CPUArchState with typedef
  cpu: Define ArchCPU
  cpu: Replace ENV_GET_CPU with env_cpu
  cpu: Introduce env_archcpu
  target/alpha: Use env_cpu, env_archcpu
  target/arm: Use env_cpu, env_archcpu
  target/cris: Use env_cpu, env_archcpu
  target/hppa: Use env_cpu, env_archcpu
  target/i386: Use env_cpu, env_archcpu
  target/lm32: Use env_cpu, env_archcpu
  target/m68k: Use env_cpu, env_archcpu
  target/microblaze: Use env_cpu, env_archcpu
  target/mips: Use env_cpu, env_archcpu
  target/moxie: Use env_cpu, env_archcpu
  target/nios2: Use env_cpu, env_archcpu
  target/openrisc: Use env_cpu, env_archcpu
  target/ppc: Use env_cpu, env_archcpu
  target/riscv: Use env_cpu, env_archcpu
  target/s390x: Use env_cpu, env_archcpu
  target/sh4: Use env_cpu, env_archcpu
  target/sparc: Use env_cpu, env_archcpu
  target/tilegx: Use env_cpu
  target/tricore: Use env_cpu
  target/unicore32: Use env_cpu, env_archcpu
  target/xtensa: Use env_cpu, env_archcpu
  cpu: Move ENV_OFFSET to exec/gen-icount.h
  cpu: Introduce CPUNegativeOffsetState
  cpu: Move icount_decr to CPUNegativeOffsetState
  cpu: Move the softmmu tlb to CPUNegativeOffsetState
  cpu: Remove CPU_COMMON
  tcg/aarch64: Use LDP to load tlb mask+table
  tcg/arm: Use LDRD to load tlb mask+table

 Makefile.target                           |   1 +
 accel/tcg/atomic_template.h               |   8 +-
 accel/tcg/softmmu_template.h              |  24 +-
 include/exec/cpu-all.h                    |  46 +++
 include/exec/cpu-defs.h                   | 113 ++++--
 include/exec/cpu_ldst.h                   |   6 +-
 include/exec/cpu_ldst_template.h          |   6 +-
 include/exec/cpu_ldst_useronly_template.h |   6 +-
 include/exec/gen-icount.h                 |  14 +-
 include/exec/softmmu-semi.h               |  16 +-
 include/qom/cpu.h                         |  28 +-
 linux-user/cpu_loop-common.h              |   2 +-
 linux-user/m68k/target_cpu.h              |   2 +-
 target/alpha/cpu-param.h                  |  19 +
 target/alpha/cpu.h                        |  40 +-
 target/arm/cpu-param.h                    |  22 ++
 target/arm/cpu.h                          |  52 +--
 target/cris/cpu-param.h                   |   5 +
 target/cris/cpu.h                         |  25 +-
 target/hppa/cpu-param.h                   |  22 ++
 target/hppa/cpu.h                         |  38 +-
 target/i386/cpu-param.h                   |  14 +
 target/i386/cpu.h                         |  40 +-
 target/lm32/cpu-param.h                   |   5 +
 target/lm32/cpu.h                         |  25 +-
 target/m68k/cpu-param.h                   |   9 +
 target/m68k/cpu.h                         |  28 +-
 target/microblaze/cpu-param.h             |   6 +
 target/microblaze/cpu.h                   |  63 ++--
 target/mips/cpu-param.h                   |  18 +
 target/mips/cpu.h                         |  21 +-
 target/mips/mips-defs.h                   |  15 -
 target/moxie/cpu-param.h                  |   5 +
 target/moxie/cpu.h                        |  29 +-
 target/nios2/cpu-param.h                  |   9 +
 target/nios2/cpu.h                        |  33 +-
 target/openrisc/cpu-param.h               |   5 +
 target/openrisc/cpu.h                     |  31 +-
 target/ppc/cpu-param.h                    |  25 ++
 target/ppc/cpu.h                          |  54 +--
 target/ppc/helper_regs.h                  |   4 +-
 target/riscv/cpu-param.h                  |  11 +
 target/riscv/cpu.h                        |  35 +-
 target/s390x/cpu-param.h                  |   5 +
 target/s390x/cpu.h                        |  31 +-
 target/sh4/cpu-param.h                    |   9 +
 target/sh4/cpu.h                          |  30 +-
 target/sparc/cpu-param.h                  |  17 +
 target/sparc/cpu.h                        |  36 +-
 target/tilegx/cpu-param.h                 |   5 +
 target/tilegx/cpu.h                       |  23 +-
 target/tricore/cpu-param.h                |   5 +
 target/tricore/cpu.h                      |  22 +-
 target/tricore/tricore-defs.h             |   5 -
 target/unicore32/cpu-param.h              |   5 +
 target/unicore32/cpu.h                    |  24 +-
 target/xtensa/cpu-param.h                 |   9 +
 target/xtensa/cpu.h                       |  40 +-
 accel/tcg/cpu-exec.c                      |  23 +-
 accel/tcg/cputlb.c                        | 193 +++++-----
 accel/tcg/tcg-all.c                       |   6 +-
 accel/tcg/tcg-runtime.c                   |   4 +-
 accel/tcg/translate-all.c                 |  10 +-
 accel/tcg/user-exec.c                     |   2 +-
 bsd-user/main.c                           |   5 +-
 bsd-user/syscall.c                        |   6 +-
 cpus.c                                    |   9 +-
 hw/i386/kvmvapic.c                        |   4 +-
 hw/i386/pc.c                              |   2 +-
 hw/intc/mips_gic.c                        |   2 +-
 hw/mips/mips_int.c                        |   2 +-
 hw/nios2/cpu_pic.c                        |   5 +-
 hw/ppc/ppc.c                              |  18 +-
 hw/ppc/ppc405_uc.c                        |   2 +-
 hw/ppc/ppc_booke.c                        |   4 +-
 hw/sparc/leon3.c                          |   4 +-
 hw/sparc/sun4m.c                          |   4 +-
 hw/sparc64/sparc64.c                      |   2 +-
 hw/unicore32/puv3.c                       |   2 +-
 hw/xtensa/pic_cpu.c                       |   2 +-
 linux-user/aarch64/cpu_loop.c             |   6 +-
 linux-user/aarch64/signal.c               |   4 +-
 linux-user/alpha/cpu_loop.c               |   2 +-
 linux-user/arm/cpu_loop.c                 |   4 +-
 linux-user/cris/cpu_loop.c                |   4 +-
 linux-user/elfload.c                      |   6 +-
 linux-user/hppa/cpu_loop.c                |   2 +-
 linux-user/i386/cpu_loop.c                |   2 +-
 linux-user/i386/signal.c                  |   2 +-
 linux-user/m68k-sim.c                     |   3 +-
 linux-user/m68k/cpu_loop.c                |   4 +-
 linux-user/main.c                         |   2 +-
 linux-user/microblaze/cpu_loop.c          |   2 +-
 linux-user/mips/cpu_loop.c                |   4 +-
 linux-user/nios2/cpu_loop.c               |   2 +-
 linux-user/openrisc/cpu_loop.c            |   2 +-
 linux-user/ppc/cpu_loop.c                 |   2 +-
 linux-user/riscv/cpu_loop.c               |   4 +-
 linux-user/s390x/cpu_loop.c               |   2 +-
 linux-user/sh4/cpu_loop.c                 |   2 +-
 linux-user/signal.c                       |   8 +-
 linux-user/sparc/cpu_loop.c               |   2 +-
 linux-user/syscall.c                      |  26 +-
 linux-user/tilegx/cpu_loop.c              |   2 +-
 linux-user/uname.c                        |   2 +-
 linux-user/vm86.c                         |  18 +-
 linux-user/xtensa/cpu_loop.c              |   2 +-
 qom/cpu-common.c                          | 425 ++++++++++++++++++++++
 qom/cpu.c                                 | 408 +--------------------
 target/alpha/helper.c                     |   8 +-
 target/alpha/sys_helper.c                 |   8 +-
 target/arm/arm-semi.c                     |   4 +-
 target/arm/cpu64.c                        |   2 +-
 target/arm/helper-a64.c                   |   4 +-
 target/arm/helper.c                       | 160 ++++----
 target/arm/op_helper.c                    |  21 +-
 target/arm/translate-a64.c                |   4 +-
 target/arm/translate.c                    |   2 +-
 target/arm/vfp_helper.c                   |   2 +-
 target/cris/mmu.c                         |   3 +-
 target/cris/op_helper.c                   |  10 +-
 target/cris/translate.c                   |   2 +-
 target/hppa/helper.c                      |   3 +-
 target/hppa/int_helper.c                  |   4 +-
 target/hppa/mem_helper.c                  |  10 +-
 target/hppa/op_helper.c                   |  10 +-
 target/i386/bpt_helper.c                  |   4 +-
 target/i386/cpu.c                         |   4 +-
 target/i386/excp_helper.c                 |   2 +-
 target/i386/fpu_helper.c                  |   2 +-
 target/i386/hax-all.c                     |   6 +-
 target/i386/helper.c                      |  16 +-
 target/i386/hvf/x86_decode.c              |  22 +-
 target/i386/hvf/x86_emu.c                 |  48 +--
 target/i386/mem_helper.c                  |   4 +-
 target/i386/misc_helper.c                 |  24 +-
 target/i386/seg_helper.c                  |  14 +-
 target/i386/smm_helper.c                  |   4 +-
 target/i386/svm_helper.c                  |  22 +-
 target/lm32/helper.c                      |  19 +-
 target/lm32/op_helper.c                   |   6 +-
 target/lm32/translate.c                   |   2 +-
 target/m68k/helper.c                      |  33 +-
 target/m68k/m68k-semi.c                   |   4 +-
 target/m68k/op_helper.c                   |  14 +-
 target/m68k/translate.c                   |   4 +-
 target/microblaze/mmu.c                   |   5 +-
 target/microblaze/op_helper.c             |   2 +-
 target/microblaze/translate.c             |   2 +-
 target/mips/helper.c                      |  15 +-
 target/mips/op_helper.c                   |  25 +-
 target/mips/translate.c                   |   3 +-
 target/mips/translate_init.inc.c          |   4 +-
 target/moxie/helper.c                     |   6 +-
 target/moxie/translate.c                  |   2 +-
 target/nios2/mmu.c                        |  14 +-
 target/nios2/op_helper.c                  |   2 +-
 target/openrisc/exception_helper.c        |   5 +-
 target/openrisc/sys_helper.c              |   8 +-
 target/ppc/excp_helper.c                  |  14 +-
 target/ppc/fpu_helper.c                   |  14 +-
 target/ppc/kvm.c                          |   5 +-
 target/ppc/misc_helper.c                  |  22 +-
 target/ppc/mmu-hash64.c                   |  14 +-
 target/ppc/mmu_helper.c                   | 116 +++---
 target/ppc/translate_init.inc.c           |  85 +++--
 target/riscv/cpu_helper.c                 |   4 +-
 target/riscv/csr.c                        |  12 +-
 target/riscv/op_helper.c                  |   8 +-
 target/s390x/cc_helper.c                  |   5 +-
 target/s390x/diag.c                       |   2 +-
 target/s390x/excp_helper.c                |   6 +-
 target/s390x/fpu_helper.c                 |   4 +-
 target/s390x/gdbstub.c                    |  24 +-
 target/s390x/helper.c                     |   7 +-
 target/s390x/int_helper.c                 |   3 +-
 target/s390x/interrupt.c                  |   6 +-
 target/s390x/mem_helper.c                 |  30 +-
 target/s390x/misc_helper.c                |  50 +--
 target/s390x/mmu_helper.c                 |   8 +-
 target/s390x/sigp.c                       |   4 +-
 target/sh4/helper.c                       |  26 +-
 target/sh4/op_helper.c                    |  11 +-
 target/sparc/fop_helper.c                 |   2 +-
 target/sparc/helper.c                     |   8 +-
 target/sparc/ldst_helper.c                |  33 +-
 target/sparc/mmu_helper.c                 |  10 +-
 target/tilegx/helper.c                    |   2 +-
 target/tricore/op_helper.c                |   4 +-
 target/unicore32/helper.c                 |   8 +-
 target/unicore32/op_helper.c              |   2 +-
 target/unicore32/softmmu.c                |  11 +-
 target/unicore32/translate.c              |  26 +-
 target/unicore32/ucf64_helper.c           |   2 +-
 target/xtensa/dbg_helper.c                |   4 +-
 target/xtensa/exc_helper.c                |   9 +-
 target/xtensa/helper.c                    |   2 +-
 target/xtensa/mmu_helper.c                |  11 +-
 target/xtensa/xtensa-semi.c               |   2 +-
 tcg/aarch64/tcg-target.inc.c              |  36 +-
 tcg/arm/tcg-target.inc.c                  | 149 +++-----
 tcg/i386/tcg-target.inc.c                 |   6 +-
 tcg/mips/tcg-target.inc.c                 |  45 +--
 tcg/ppc/tcg-target.inc.c                  |  32 +-
 tcg/riscv/tcg-target.inc.c                |  37 +-
 tcg/s390/tcg-target.inc.c                 |  13 +-
 tcg/sparc/tcg-target.inc.c                |  40 +-
 docs/devel/tracing.txt                    |   4 +-
 qom/Makefile.objs                         |   2 +-
 scripts/tracetool/format/tcg_helper_c.py  |   2 +-
 210 files changed, 1841 insertions(+), 2256 deletions(-)
 create mode 100644 target/alpha/cpu-param.h
 create mode 100644 target/arm/cpu-param.h
 create mode 100644 target/cris/cpu-param.h
 create mode 100644 target/hppa/cpu-param.h
 create mode 100644 target/i386/cpu-param.h
 create mode 100644 target/lm32/cpu-param.h
 create mode 100644 target/m68k/cpu-param.h
 create mode 100644 target/microblaze/cpu-param.h
 create mode 100644 target/mips/cpu-param.h
 create mode 100644 target/moxie/cpu-param.h
 create mode 100644 target/nios2/cpu-param.h
 create mode 100644 target/openrisc/cpu-param.h
 create mode 100644 target/ppc/cpu-param.h
 create mode 100644 target/riscv/cpu-param.h
 create mode 100644 target/s390x/cpu-param.h
 create mode 100644 target/sh4/cpu-param.h
 create mode 100644 target/sparc/cpu-param.h
 create mode 100644 target/tilegx/cpu-param.h
 create mode 100644 target/tricore/cpu-param.h
 create mode 100644 target/unicore32/cpu-param.h
 create mode 100644 target/xtensa/cpu-param.h
 create mode 100644 qom/cpu-common.c

-- 
2.17.1

Comments

no-reply@patchew.org March 23, 2019, 7:58 p.m. UTC | #1
Patchew URL: https://patchew.org/QEMU/20190323190925.21324-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 20190323190925.21324-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH for-4.1 00/35] tcg: Move the softmmu tlb to CPUNegativeOffsetState
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]               patchew/20190323190925.21324-1-richard.henderson@linaro.org -> patchew/20190323190925.21324-1-richard.henderson@linaro.org
Switched to a new branch 'test'
d1700d8105 tcg/arm: Use LDRD to load tlb mask+table
6fea5a55f5 tcg/aarch64: Use LDP to load tlb mask+table
c58058146b cpu: Remove CPU_COMMON
baea823f37 cpu: Move the softmmu tlb to CPUNegativeOffsetState
ea517fda54 cpu: Move icount_decr to CPUNegativeOffsetState
5a9eb19210 cpu: Introduce CPUNegativeOffsetState
e6935da753 cpu: Move ENV_OFFSET to exec/gen-icount.h
9e9500704a target/xtensa: Use env_cpu, env_archcpu
7465342e22 target/unicore32: Use env_cpu, env_archcpu
83ee4b5455 target/tricore: Use env_cpu
f387cedb3b target/tilegx: Use env_cpu
5d95e6b049 target/sparc: Use env_cpu, env_archcpu
1bbc50511a target/sh4: Use env_cpu, env_archcpu
2b66e665c0 target/s390x: Use env_cpu, env_archcpu
de2caf9480 target/riscv: Use env_cpu, env_archcpu
16d5ab98ff target/ppc: Use env_cpu, env_archcpu
e351a3dec1 target/openrisc: Use env_cpu, env_archcpu
f0af08e73f target/nios2: Use env_cpu, env_archcpu
4608db3d65 target/moxie: Use env_cpu, env_archcpu
d5e7d2e3f4 target/mips: Use env_cpu, env_archcpu
4333c56896 target/microblaze: Use env_cpu, env_archcpu
faae7b3fc7 target/m68k: Use env_cpu, env_archcpu
40082bea4d target/lm32: Use env_cpu, env_archcpu
9f01e6f34b target/i386: Use env_cpu, env_archcpu
4cebac8128 target/hppa: Use env_cpu, env_archcpu
3a51d8c72c target/cris: Use env_cpu, env_archcpu
d34fb24a61 target/arm: Use env_cpu, env_archcpu
815a46f2d4 target/alpha: Use env_cpu, env_archcpu
2014d9c385 cpu: Introduce env_archcpu
aaa0acc53e cpu: Replace ENV_GET_CPU with env_cpu
85d89e6f2b cpu: Define ArchCPU
d0b5a94824 cpu: Define CPUArchState with typedef
b034922803 tcg: Create struct CPUTLB
763b65c081 tcg: Split out target/arch/cpu-param.h
4cb187a892 tcg: Fold CPUTLBWindow into CPUTLBDesc

=== OUTPUT BEGIN ===
1/35 Checking commit 4cb187a892e5 (tcg: Fold CPUTLBWindow into CPUTLBDesc)
2/35 Checking commit 763b65c08108 (tcg: Split out target/arch/cpu-param.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#55: 
new file mode 100644

WARNING: Block comments use a leading /* on a separate line
#356: FILE: target/i386/cpu-param.h:4:
+/* ??? This is really 48 bits, sign-extended, but the only thing

WARNING: Block comments use * on subsequent lines
#357: FILE: target/i386/cpu-param.h:5:
+/* ??? This is really 48 bits, sign-extended, but the only thing
+   accessible to userland with bit 48 set is the VSYSCALL, and that

WARNING: Block comments use a trailing */ on a separate line
#358: FILE: target/i386/cpu-param.h:6:
+   is handled via other mechanisms.  */

WARNING: Block comments use a leading /* on a separate line
#465: FILE: target/m68k/cpu-param.h:2:
+/* Coldfire Linux uses 8k pages

ERROR: code indent should never use tabs
#1023: FILE: target/sh4/cpu-param.h:2:
+#define TARGET_PAGE_BITS 12^I/* 4k */$

total: 1 errors, 5 warnings, 1030 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit b03492280352 (tcg: Create struct CPUTLB)
WARNING: line over 80 characters
#349: FILE: accel/tcg/cputlb.c:781:
+        env_tlb(env)->d[mmu_idx].viotlb[vidx] = env_tlb(env)->d[mmu_idx].iotlb[index];

total: 0 errors, 1 warnings, 677 lines checked

Patch 3/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/35 Checking commit d0b5a9482459 (cpu: Define CPUArchState with typedef)
5/35 Checking commit 85d89e6f2b8d (cpu: Define ArchCPU)
6/35 Checking commit aaa0acc53e5f (cpu: Replace ENV_GET_CPU with env_cpu)
WARNING: line over 80 characters
#1191: FILE: target/i386/hvf/x86_emu.c:412:
+        hvf_handle_io(env_cpu(env), DX(env), &RAX(env), 1, decode->operand_size, 1);

WARNING: line over 80 characters
#1204: FILE: target/i386/hvf/x86_emu.c:429:
+        hvf_handle_io(env_cpu(env), decode->op[0].val, &val, 0, decode->operand_size, 1);

WARNING: line over 80 characters
#1226: FILE: target/i386/hvf/x86_emu.c:487:
+    target_ulong addr = linear_addr_size(env_cpu(env), RDI(env), decode->addressing_size,

WARNING: line over 80 characters
#1233: FILE: target/i386/hvf/x86_emu.c:492:
+    vmx_write_mem(env_cpu(env), addr, env->hvf_emul->mmio_buf, decode->operand_size);

WARNING: line over 80 characters
#1243: FILE: target/i386/hvf/x86_emu.c:512:
+    vmx_read_mem(env_cpu(env), env->hvf_emul->mmio_buf, addr, decode->operand_size);

WARNING: line over 80 characters
#1271: FILE: target/i386/hvf/x86_emu.c:594:
+    addr = linear_addr_size(env_cpu(env), RDI(env), decode->addressing_size, R_ES);

WARNING: line over 80 characters
#1283: FILE: target/i386/hvf/x86_emu.c:617:
+    addr = linear_addr_size(env_cpu(env), RDI(env), decode->addressing_size, R_ES);

total: 0 errors, 7 warnings, 1318 lines checked

Patch 6/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/35 Checking commit 2014d9c38562 (cpu: Introduce env_archcpu)
8/35 Checking commit 815a46f2d450 (target/alpha: Use env_cpu, env_archcpu)
9/35 Checking commit d34fb24a61f8 (target/arm: Use env_cpu, env_archcpu)
10/35 Checking commit 3a51d8c72c9f (target/cris: Use env_cpu, env_archcpu)
ERROR: suspect code indent for conditional statements (24, 16)
#96: FILE: target/cris/op_helper.c:141:
                        if (tlb_v) {
+                tlb_flush_page(env_cpu(env), vaddr);

total: 1 errors, 0 warnings, 76 lines checked

Patch 10/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

11/35 Checking commit 4cebac812828 (target/hppa: Use env_cpu, env_archcpu)
12/35 Checking commit 9f01e6f34b4d (target/i386: Use env_cpu, env_archcpu)
13/35 Checking commit 40082bea4d7f (target/lm32: Use env_cpu, env_archcpu)
14/35 Checking commit faae7b3fc73c (target/m68k: Use env_cpu, env_archcpu)
15/35 Checking commit 4333c568969e (target/microblaze: Use env_cpu, env_archcpu)
16/35 Checking commit d5e7d2e3f4f4 (target/mips: Use env_cpu, env_archcpu)
17/35 Checking commit 4608db3d6541 (target/moxie: Use env_cpu, env_archcpu)
18/35 Checking commit f0af08e73fcd (target/nios2: Use env_cpu, env_archcpu)
19/35 Checking commit e351a3dec1bf (target/openrisc: Use env_cpu, env_archcpu)
20/35 Checking commit 16d5ab98ffbb (target/ppc: Use env_cpu, env_archcpu)
WARNING: line over 80 characters
#549: FILE: target/ppc/mmu_helper.c:741:
+        cpu_abort(env_cpu(env), "Little-endian regions are not supported by now\n");

WARNING: line over 80 characters
#616: FILE: target/ppc/mmu_helper.c:1454:
+            cpu_abort(env_cpu(env), "PowerPC in real mode do not do any translation\n");

WARNING: line over 80 characters
#1073: FILE: target/ppc/translate_init.inc.c:4849:
+        cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);

WARNING: line over 80 characters
#1082: FILE: target/ppc/translate_init.inc.c:4873:
+        cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);

total: 0 errors, 4 warnings, 1149 lines checked

Patch 20/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/35 Checking commit de2caf948058 (target/riscv: Use env_cpu, env_archcpu)
22/35 Checking commit 2b66e665c0c7 (target/s390x: Use env_cpu, env_archcpu)
23/35 Checking commit 1bbc50511a30 (target/sh4: Use env_cpu, env_archcpu)
24/35 Checking commit 5d95e6b0494c (target/sparc: Use env_cpu, env_archcpu)
25/35 Checking commit f387cedb3b98 (target/tilegx: Use env_cpu)
26/35 Checking commit 83ee4b5455dc (target/tricore: Use env_cpu)
27/35 Checking commit 7465342e22c8 (target/unicore32: Use env_cpu, env_archcpu)
28/35 Checking commit 9e9500704afd (target/xtensa: Use env_cpu, env_archcpu)
29/35 Checking commit e6935da75399 (cpu: Move ENV_OFFSET to exec/gen-icount.h)
30/35 Checking commit 5a9eb192102c (cpu: Introduce CPUNegativeOffsetState)
31/35 Checking commit ea517fda548e (cpu: Move icount_decr to CPUNegativeOffsetState)
ERROR: return is not a function, parentheses are not required
#206: FILE: cpus.c:240:
+    return (cpu->icount_budget -

WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#381: 
new file mode 100644

WARNING: Block comments use a leading /* on a separate line
#482: FILE: qom/cpu-common.c:97:
+/* Resetting the IRQ comes from across the code base so we take the

WARNING: Block comments use a trailing */ on a separate line
#483: FILE: qom/cpu-common.c:98:
+ * BQL here if we need to.  cpu_interrupt assumes it is held.*/

WARNING: Block comments use a leading /* on a separate line
#568: FILE: qom/cpu-common.c:183:
+    /* If no extra check is required, QEMU watchpoint match can be considered

WARNING: Block comments use a leading /* on a separate line
#680: FILE: qom/cpu-common.c:295:
+    /* qdev_get_machine() can return something that's not TYPE_MACHINE

total: 1 errors, 5 warnings, 970 lines checked

Patch 31/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

32/35 Checking commit baea823f3758 (cpu: Move the softmmu tlb to CPUNegativeOffsetState)
ERROR: trailing whitespace
#202: FILE: tcg/i386/tcg-target.inc.c:1657:
+                         TLB_MASK_TABLE_OFS(mem_index) + $

ERROR: trailing whitespace
#207: FILE: tcg/i386/tcg-target.inc.c:1661:
+                         TLB_MASK_TABLE_OFS(mem_index) + $

total: 2 errors, 0 warnings, 395 lines checked

Patch 32/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

33/35 Checking commit c58058146b25 (cpu: Remove CPU_COMMON)
34/35 Checking commit 6fea5a55f568 (tcg/aarch64: Use LDP to load tlb mask+table)
35/35 Checking commit d1700d810526 (tcg/arm: Use LDRD to load tlb mask+table)
ERROR: code indent should never use tabs
#113: FILE: tcg/arm/tcg-target.inc.c:1289:
+^I^I        TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0);$

ERROR: code indent should never use tabs
#118: FILE: tcg/arm/tcg-target.inc.c:1294:
+^I}$

total: 2 errors, 0 warnings, 133 lines checked

Patch 35/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190323190925.21324-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
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