mbox series

[00/16] hw/mips: Set CPU frequency

Message ID 20200928171539.788309-1-f4bug@amsat.org
Headers show
Series hw/mips: Set CPU frequency | expand

Message

Philippe Mathieu-Daudé Sept. 28, 2020, 5:15 p.m. UTC
All the MIPS cores emulated by QEMU provides the Coproc#0
'Count' register which can be used as a free running timer.

Since it's introduction in 2005 this timer uses a fixed
frequency of 100 MHz (for a CPU freq of 200 MHz).
While this is not an issue with Linux guests, it makes
some firmwares behave incorrectly.

The Clock API allow propagating clocks. It is particularly
useful when hardware dynamicly changes clock frequencies.

To be able to model such MIPS hardware, we need to refactor
the MIPS hardware code to handle clocks.

This series is organized as follow:

- let all CPU have an input clock,
- MIPS CPU get an input clock
- when the clock is changed, CP0 timer is updated
- set correct CPU frequencies to all boards
- do not allow MIPS CPU without input clock

I used a MIPSsim test suggested by Thomas. It is also included
as bonus at the end.

Possible follow up:
- QOM'ify the GIC
- let the GIC handle dynamic clock changes

Regards,

Phil.

Philippe Mathieu-Daudé (16):
  hw/core/cpu: Let CPU object have a clock source
  target/mips: Move cpu_mips_get_random() with CP0 helpers
  target/mips/cp0_timer: Explicit unit in variable name
  target/mips/cpu: Introduce mips_cpu_properties[]
  target/mips/cpu: Set default CPU frequency to 200 MHz
  target/mips: Keep CP0 counter in sync with the CPU frequency
  hw/mips/r4k: Explicit CPU frequency is 200 MHz
  hw/mips/fuloong2e: Set CPU frequency to 533 MHz
  hw/mips/mipssim: Correct CPU frequency
  hw/mips/jazz: Correct CPU frequencies
  hw/mips/cps: Expose input clock and connect it to CPU cores
  hw/mips/boston: Set CPU frequency to 1 GHz
  hw/mips/malta: Set CPU frequency to 320 MHz
  hw/mips/cps: Do not allow use without input clock
  target/mips/cpu: Do not allow system-mode use without input clock
  tests/acceptance: Test the MIPSsim machine

 include/hw/core/cpu.h                    |  5 +++
 include/hw/mips/cps.h                    |  2 +
 target/mips/cpu.h                        |  9 ++++
 target/mips/internal.h                   |  2 +-
 hw/core/cpu.c                            | 12 +++++
 hw/mips/boston.c                         | 13 ++++++
 hw/mips/cps.c                            |  8 ++++
 hw/mips/fuloong2e.c                      |  8 +++-
 hw/mips/jazz.c                           | 16 ++++++-
 hw/mips/malta.c                          | 20 +++++++--
 hw/mips/mipssim.c                        | 12 ++++-
 hw/mips/r4k.c                            |  8 +++-
 target/mips/cp0_helper.c                 | 25 +++++++++++
 target/mips/cp0_timer.c                  | 51 ++++++---------------
 target/mips/cpu.c                        | 43 +++++++++++++++++-
 MAINTAINERS                              |  1 +
 tests/acceptance/machine_mips_mipssim.py | 56 ++++++++++++++++++++++++
 17 files changed, 244 insertions(+), 47 deletions(-)
 create mode 100644 tests/acceptance/machine_mips_mipssim.py

Comments

no-reply@patchew.org Sept. 29, 2020, 2:46 a.m. UTC | #1
Patchew URL: https://patchew.org/QEMU/20200928171539.788309-1-f4bug@amsat.org/



Hi,

This series failed the docker-quick@centos7 build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

=== TEST SCRIPT BEGIN ===
#!/bin/bash
make docker-image-centos7 V=1 NETWORK=1
time make docker-test-quick@centos7 SHOW_ENV=1 J=14 NETWORK=1
=== TEST SCRIPT END ===

C linker for the host machine: cc ld.bfd 2.27-43
Host machine cpu family: x86_64
Host machine cpu: x86_64
../src/meson.build:10: WARNING: Module unstable-keyval has no backwards or forwards compatibility and might not exist in future releases.
Program sh found: YES
Program python3 found: YES (/usr/bin/python3)
Configuring ninjatool using configuration
---
qemu-system-aarch64: falling back to tcg
socket_accept failed: Resource temporarily unavailable
**
ERROR:../src/tests/qtest/libqtest.c:301:qtest_init_without_qmp_handshake: assertion failed: (s->fd >= 0 && s->qmp_fd >= 0)
../src/tests/qtest/libqtest.c:166: kill_qemu() tried to terminate QEMU process but encountered exit status 1 (expected 0)
  TEST    iotest-qcow2: 013
ERROR qtest-x86_64: pxe-test - Bail out! ERROR:../src/tests/qtest/libqtest.c:301:qtest_init_without_qmp_handshake: assertion failed: (s->fd >= 0 && s->qmp_fd >= 0)
make: *** [run-test-110] Error 1
make: *** Waiting for unfinished jobs....

Looking for expected file 'tests/data/acpi/virt/FACP.numamem'
---
    raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sudo', '-n', 'docker', 'run', '--rm', '--label', 'com.qemu.instance.uuid=e2cdd463ef8a4c2f9b9143e69d8ac437', '-u', '1003', '--security-opt', 'seccomp=unconfined', '-e', 'TARGET_LIST=', '-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=14', '-e', 'DEBUG=', '-e', 'SHOW_ENV=1', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', '/home/patchew2/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', '/var/tmp/patchew-tester-tmp-9dln7e0v/src/docker-src.2020-09-28-22.27.36.11269:/var/tmp/qemu:z,ro', 'qemu/centos7', '/var/tmp/qemu/run', 'test-quick']' returned non-zero exit status 2.
filter=--filter=label=com.qemu.instance.uuid=e2cdd463ef8a4c2f9b9143e69d8ac437
make[1]: *** [docker-run] Error 1
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-9dln7e0v/src'
make: *** [docker-run-test-quick@centos7] Error 2

real    18m49.678s
user    0m13.756s


The full log is available at
http://patchew.org/logs/20200928171539.788309-1-f4bug@amsat.org/testing.docker-quick@centos7/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
Philippe Mathieu-Daudé Sept. 29, 2020, 8:58 a.m. UTC | #2
On 9/29/20 4:46 AM, no-reply@patchew.org wrote:
> Patchew URL: https://patchew.org/QEMU/20200928171539.788309-1-f4bug@amsat.org/

> time make docker-test-quick@centos7 SHOW_ENV=1 J=14 NETWORK=1

> ---

> qemu-system-aarch64: falling back to tcg

> socket_accept failed: Resource temporarily unavailable

> **

> ERROR:../src/tests/qtest/libqtest.c:301:qtest_init_without_qmp_handshake: assertion failed: (s->fd >= 0 && s->qmp_fd >= 0)


Unrelated to this series, as it is only MIPS.

> ../src/tests/qtest/libqtest.c:166: kill_qemu() tried to terminate QEMU process but encountered exit status 1 (expected 0)

>   TEST    iotest-qcow2: 013

> ERROR qtest-x86_64: pxe-test - Bail out! ERROR:../src/tests/qtest/libqtest.c:301:qtest_init_without_qmp_handshake: assertion failed: (s->fd >= 0 && s->qmp_fd >= 0)

> make: *** [run-test-110] Error 1

> make: *** Waiting for unfinished jobs....

> 

> Looking for expected file 'tests/data/acpi/virt/FACP.numamem'

> ---

> real    18m49.678s

> user    0m13.756s

> 

> 

> The full log is available at

> http://patchew.org/logs/20200928171539.788309-1-f4bug@amsat.org/testing.docker-quick@centos7/?type=message.

> ---
Igor Mammedov Sept. 30, 2020, 7:40 a.m. UTC | #3
On Mon, 28 Sep 2020 19:15:23 +0200
Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:

> All the MIPS cores emulated by QEMU provides the Coproc#0

> 'Count' register which can be used as a free running timer.

> 

> Since it's introduction in 2005 this timer uses a fixed

> frequency of 100 MHz (for a CPU freq of 200 MHz).

> While this is not an issue with Linux guests, it makes

> some firmwares behave incorrectly.

> 

> The Clock API allow propagating clocks. It is particularly

> useful when hardware dynamicly changes clock frequencies.

> 

> To be able to model such MIPS hardware, we need to refactor

> the MIPS hardware code to handle clocks.

> 

> This series is organized as follow:

> 

> - let all CPU have an input clock,

> - MIPS CPU get an input clock

> - when the clock is changed, CP0 timer is updated

> - set correct CPU frequencies to all boards

> - do not allow MIPS CPU without input clock


is this clock an integral part of MIPS cpus or it's an external device?

> I used a MIPSsim test suggested by Thomas. It is also included

> as bonus at the end.

> 

> Possible follow up:

> - QOM'ify the GIC

> - let the GIC handle dynamic clock changes

> 

> Regards,

> 

> Phil.

> 

> Philippe Mathieu-Daudé (16):

>   hw/core/cpu: Let CPU object have a clock source

>   target/mips: Move cpu_mips_get_random() with CP0 helpers

>   target/mips/cp0_timer: Explicit unit in variable name

>   target/mips/cpu: Introduce mips_cpu_properties[]

>   target/mips/cpu: Set default CPU frequency to 200 MHz

>   target/mips: Keep CP0 counter in sync with the CPU frequency

>   hw/mips/r4k: Explicit CPU frequency is 200 MHz

>   hw/mips/fuloong2e: Set CPU frequency to 533 MHz

>   hw/mips/mipssim: Correct CPU frequency

>   hw/mips/jazz: Correct CPU frequencies

>   hw/mips/cps: Expose input clock and connect it to CPU cores

>   hw/mips/boston: Set CPU frequency to 1 GHz

>   hw/mips/malta: Set CPU frequency to 320 MHz

>   hw/mips/cps: Do not allow use without input clock

>   target/mips/cpu: Do not allow system-mode use without input clock

>   tests/acceptance: Test the MIPSsim machine

> 

>  include/hw/core/cpu.h                    |  5 +++

>  include/hw/mips/cps.h                    |  2 +

>  target/mips/cpu.h                        |  9 ++++

>  target/mips/internal.h                   |  2 +-

>  hw/core/cpu.c                            | 12 +++++

>  hw/mips/boston.c                         | 13 ++++++

>  hw/mips/cps.c                            |  8 ++++

>  hw/mips/fuloong2e.c                      |  8 +++-

>  hw/mips/jazz.c                           | 16 ++++++-

>  hw/mips/malta.c                          | 20 +++++++--

>  hw/mips/mipssim.c                        | 12 ++++-

>  hw/mips/r4k.c                            |  8 +++-

>  target/mips/cp0_helper.c                 | 25 +++++++++++

>  target/mips/cp0_timer.c                  | 51 ++++++---------------

>  target/mips/cpu.c                        | 43 +++++++++++++++++-

>  MAINTAINERS                              |  1 +

>  tests/acceptance/machine_mips_mipssim.py | 56 ++++++++++++++++++++++++

>  17 files changed, 244 insertions(+), 47 deletions(-)

>  create mode 100644 tests/acceptance/machine_mips_mipssim.py

>
Philippe Mathieu-Daudé Sept. 30, 2020, 10:13 a.m. UTC | #4
On 9/30/20 9:40 AM, Igor Mammedov wrote:
> On Mon, 28 Sep 2020 19:15:23 +0200

> Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:

> 

>> All the MIPS cores emulated by QEMU provides the Coproc#0

>> 'Count' register which can be used as a free running timer.

>>

>> Since it's introduction in 2005 this timer uses a fixed

>> frequency of 100 MHz (for a CPU freq of 200 MHz).

>> While this is not an issue with Linux guests, it makes

>> some firmwares behave incorrectly.

>>

>> The Clock API allow propagating clocks. It is particularly

>> useful when hardware dynamicly changes clock frequencies.

>>

>> To be able to model such MIPS hardware, we need to refactor

>> the MIPS hardware code to handle clocks.

>>

>> This series is organized as follow:

>>

>> - let all CPU have an input clock,

>> - MIPS CPU get an input clock

>> - when the clock is changed, CP0 timer is updated

>> - set correct CPU frequencies to all boards

>> - do not allow MIPS CPU without input clock

> 

> is this clock an integral part of MIPS cpus or it's an external device?


CPU cores are clocked via an external clock.
This clock can be on the board (from a crystal oscillator to
complex PLL) or on-chip for some system-on-chip.

In all the (current) QEMU MIPS machines it is external although.

Regards,

Phil.
Philippe Mathieu-Daudé Oct. 9, 2020, 3:40 p.m. UTC | #5
On 9/28/20 7:15 PM, Philippe Mathieu-Daudé wrote:
> All the MIPS cores emulated by QEMU provides the Coproc#0

> 'Count' register which can be used as a free running timer.

> 

> Since it's introduction in 2005 this timer uses a fixed

> frequency of 100 MHz (for a CPU freq of 200 MHz).

> While this is not an issue with Linux guests, it makes

> some firmwares behave incorrectly.

> 

> The Clock API allow propagating clocks. It is particularly

> useful when hardware dynamicly changes clock frequencies.

> 

> To be able to model such MIPS hardware, we need to refactor

> the MIPS hardware code to handle clocks.

> 

> This series is organized as follow:

> 

> - let all CPU have an input clock,

> - MIPS CPU get an input clock

> - when the clock is changed, CP0 timer is updated

> - set correct CPU frequencies to all boards

> - do not allow MIPS CPU without input clock

> 

> I used a MIPSsim test suggested by Thomas. It is also included

> as bonus at the end.

> 

> Possible follow up:

> - QOM'ify the GIC

> - let the GIC handle dynamic clock changes

> 

> Regards,

> 

> Phil.

> 

> Philippe Mathieu-Daudé (16):

>    hw/core/cpu: Let CPU object have a clock source

>    target/mips: Move cpu_mips_get_random() with CP0 helpers

>    target/mips/cp0_timer: Explicit unit in variable name

>    target/mips/cpu: Introduce mips_cpu_properties[]

>    target/mips/cpu: Set default CPU frequency to 200 MHz

>    target/mips: Keep CP0 counter in sync with the CPU frequency

>    hw/mips/r4k: Explicit CPU frequency is 200 MHz

>    hw/mips/fuloong2e: Set CPU frequency to 533 MHz

>    hw/mips/mipssim: Correct CPU frequency

>    hw/mips/jazz: Correct CPU frequencies

>    hw/mips/cps: Expose input clock and connect it to CPU cores

>    hw/mips/boston: Set CPU frequency to 1 GHz

>    hw/mips/malta: Set CPU frequency to 320 MHz

>    hw/mips/cps: Do not allow use without input clock

>    target/mips/cpu: Do not allow system-mode use without input clock

>    tests/acceptance: Test the MIPSsim machine


I'm queuing patches 2 and 3 to mips-next. The others depend
of #1 which has been asked for changes.

Thanks,

Phil.