| Message ID | 20201022080440.10069-1-space.monkey.delivers@gmail.com |
|---|---|
| Headers | show |
| Series | RISC-V Pointer Masking implementation | expand |
On Thu, Oct 22, 2020 at 1:04 AM Alexey Baturo <baturo.alexey@gmail.com> wrote: > > Hi, > > Added missing sign-off on the first patch. > > Thanks > > Alexey Baturo (5): > [RISCV_PM] Add J-extension into RISC-V > [RISCV_PM] Support CSRs required for RISC-V PM extension except for > ones in hypervisor mode > [RISCV_PM] Print new PM CSRs in QEMU logs > [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of > instructions > [RISCV_PM] Allow experimental J-ext to be turned on > > Anatoly Parshintsev (1): > [RISCV_PM] Implement address masking functions required for RISC-V > Pointer Masking extension Thanks for the patches! I don't know a lot about the J-extension, so it will take me some time to read into it before I can review this. Maybe you can convince Richard to review it for you :P Alistair > > target/riscv/cpu.c | 30 +++ > target/riscv/cpu.h | 33 +++ > target/riscv/cpu_bits.h | 66 ++++++ > target/riscv/csr.c | 271 ++++++++++++++++++++++++ > target/riscv/insn_trans/trans_rva.c.inc | 3 + > target/riscv/insn_trans/trans_rvd.c.inc | 2 + > target/riscv/insn_trans/trans_rvf.c.inc | 2 + > target/riscv/insn_trans/trans_rvi.c.inc | 2 + > target/riscv/translate.c | 44 ++++ > 9 files changed, 453 insertions(+) > > -- > 2.20.1 > >
On 10/23/20 5:25 PM, Alistair Francis wrote: > On Thu, Oct 22, 2020 at 1:04 AM Alexey Baturo <baturo.alexey@gmail.com> wrote: >> >> Hi, >> >> Added missing sign-off on the first patch. >> >> Thanks >> >> Alexey Baturo (5): >> [RISCV_PM] Add J-extension into RISC-V >> [RISCV_PM] Support CSRs required for RISC-V PM extension except for >> ones in hypervisor mode >> [RISCV_PM] Print new PM CSRs in QEMU logs >> [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of >> instructions >> [RISCV_PM] Allow experimental J-ext to be turned on >> >> Anatoly Parshintsev (1): >> [RISCV_PM] Implement address masking functions required for RISC-V >> Pointer Masking extension > > Thanks for the patches! > > I don't know a lot about the J-extension, so it will take me some time > to read into it before I can review this. > > Maybe you can convince Richard to review it for you :P Richard did review v3. Alexey seems to have misplaced or not added the r-b tags. Although I missed that it misses the mask for the special hypervisor load/store insns? r~
Hi, Added missing sign-off on the first patch. Thanks Alexey Baturo (5): [RISCV_PM] Add J-extension into RISC-V [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode [RISCV_PM] Print new PM CSRs in QEMU logs [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions [RISCV_PM] Allow experimental J-ext to be turned on Anatoly Parshintsev (1): [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension target/riscv/cpu.c | 30 +++ target/riscv/cpu.h | 33 +++ target/riscv/cpu_bits.h | 66 ++++++ target/riscv/csr.c | 271 ++++++++++++++++++++++++ target/riscv/insn_trans/trans_rva.c.inc | 3 + target/riscv/insn_trans/trans_rvd.c.inc | 2 + target/riscv/insn_trans/trans_rvf.c.inc | 2 + target/riscv/insn_trans/trans_rvi.c.inc | 2 + target/riscv/translate.c | 44 ++++ 9 files changed, 453 insertions(+)