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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id u12sm2010pfh.98.2021.01.05.09.19.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 09:19:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 00/43] Mirror map JIT memory for TCG Date: Tue, 5 Jan 2021 07:19:07 -1000 Message-Id: <20210105171950.415486-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Joelle van Dyne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Changes for v5: * Protect MAP_JIT with !splitwx. * Improve comments for in_code_gen_buffer. * Update qemu-options.hx. Thanks to Joelle for all of the reviews on v4. The patches still without review are: 17-tcg-Add-accel-tcg-split-wx-property.patch 27-tcg-ppc-Use-tcg_tbrel_diff.patch 28-tcg-ppc-Use-tcg_out_mem_long-to-reset-TCG_REG_TB.patch 29-tcg-ppc-Support-split-wx-code-generation.patch 30-tcg-sparc-Use-tcg_tbrel_diff.patch 31-tcg-sparc-Support-split-wx-code-generation.patch 32-tcg-s390-Use-tcg_tbrel_diff.patch 33-tcg-s390-Support-split-wx-code-generation.patch 37-accel-tcg-Add-mips-support-to-alloc_code_gen_buff.patch 38-tcg-mips-Do-not-assert-on-relocation-overflow.patch 39-tcg-mips-Support-split-wx-code-generation.patch 40-tcg-arm-Support-split-wx-code-generation.patch I'll be happy with even a glance and an Acked-by across some of these non-x86 tcg backends, just to see if I've done something obviously wrong. r~ Cc: Philippe Mathieu-Daudé Cc: Alex Bennée Cc: Joelle van Dyne Richard Henderson (43): tcg: Do not flush icache for interpreter util: Extract flush_icache_range to cacheflush.c util: Enhance flush_icache_range with separate data pointer util: Specialize flush_idcache_range for aarch64 tcg: Move tcg prologue pointer out of TCGContext tcg: Move tcg epilogue pointer out of TCGContext tcg: Add in_code_gen_buffer tcg: Introduce tcg_splitwx_to_{rx,rw} tcg: Adjust TCGLabel for const tcg: Adjust tcg_out_call for const tcg: Adjust tcg_out_label for const tcg: Adjust tcg_register_jit for const tcg: Adjust tb_target_set_jmp_target for split-wx tcg: Make DisasContextBase.tb const tcg: Make tb arg to synchronize_from_tb const tcg: Use Error with alloc_code_gen_buffer tcg: Add --accel tcg,split-wx property accel/tcg: Support split-wx for linux with memfd accel/tcg: Support split-wx for darwin/iOS with vm_remap tcg: Return the TB pointer from the rx region from exit_tb tcg/i386: Support split-wx code generation tcg/aarch64: Use B not BL for tcg_out_goto_long tcg/aarch64: Support split-wx code generation disas: Push const down through host disassembly tcg/tci: Push const down through bytecode reading tcg: Introduce tcg_tbrel_diff tcg/ppc: Use tcg_tbrel_diff tcg/ppc: Use tcg_out_mem_long to reset TCG_REG_TB tcg/ppc: Support split-wx code generation tcg/sparc: Use tcg_tbrel_diff tcg/sparc: Support split-wx code generation tcg/s390: Use tcg_tbrel_diff tcg/s390: Support split-wx code generation tcg/riscv: Fix branch range checks tcg/riscv: Remove branch-over-branch fallback tcg/riscv: Support split-wx code generation accel/tcg: Add mips support to alloc_code_gen_buffer_splitwx_memfd tcg/mips: Do not assert on relocation overflow tcg/mips: Support split-wx code generation tcg/arm: Support split-wx code generation tcg: Remove TCG_TARGET_SUPPORT_MIRROR tcg: Constify tcg_code_gen_epilogue tcg: Constify TCGLabelQemuLdst.raddr accel/tcg/tcg-runtime.h | 2 +- include/disas/dis-asm.h | 4 +- include/disas/disas.h | 2 +- include/exec/exec-all.h | 2 +- include/exec/gen-icount.h | 4 +- include/exec/log.h | 2 +- include/exec/translator.h | 2 +- include/hw/core/cpu.h | 3 +- include/qemu/cacheflush.h | 35 ++++ include/sysemu/tcg.h | 3 +- include/tcg/tcg-op.h | 2 +- include/tcg/tcg.h | 61 +++++-- tcg/aarch64/tcg-target.h | 7 +- tcg/arm/tcg-target.h | 7 +- tcg/i386/tcg-target.h | 10 +- tcg/mips/tcg-target.h | 13 +- tcg/ppc/tcg-target.h | 3 +- tcg/riscv/tcg-target.h | 7 +- tcg/s390/tcg-target.h | 12 +- tcg/sparc/tcg-target.h | 10 +- tcg/tci/tcg-target.h | 10 +- accel/tcg/cpu-exec.c | 41 +++-- accel/tcg/tcg-all.c | 26 ++- accel/tcg/tcg-runtime.c | 4 +- accel/tcg/translate-all.c | 311 +++++++++++++++++++++++++++-------- accel/tcg/translator.c | 4 +- bsd-user/main.c | 2 +- disas.c | 2 +- disas/capstone.c | 2 +- linux-user/main.c | 2 +- softmmu/physmem.c | 3 +- target/arm/cpu.c | 3 +- target/arm/translate-a64.c | 2 +- target/avr/cpu.c | 3 +- target/hppa/cpu.c | 3 +- target/i386/tcg/tcg-cpu.c | 3 +- target/microblaze/cpu.c | 3 +- target/mips/cpu.c | 3 +- target/riscv/cpu.c | 3 +- target/rx/cpu.c | 3 +- target/sh4/cpu.c | 3 +- target/sparc/cpu.c | 3 +- target/tricore/cpu.c | 2 +- tcg/tcg-op.c | 15 +- tcg/tcg.c | 91 ++++++++-- tcg/tci.c | 60 ++++--- util/cacheflush.c | 146 ++++++++++++++++ util/cacheinfo.c | 8 +- tcg/aarch64/tcg-target.c.inc | 75 +++++---- tcg/arm/tcg-target.c.inc | 41 ++--- tcg/i386/tcg-target.c.inc | 36 ++-- tcg/mips/tcg-target.c.inc | 97 +++++------ tcg/ppc/tcg-target.c.inc | 110 ++++++------- tcg/riscv/tcg-target.c.inc | 125 +++++--------- tcg/s390/tcg-target.c.inc | 91 +++++----- tcg/sparc/tcg-target.c.inc | 58 +++---- tcg/tcg-ldst.c.inc | 2 +- tcg/tcg-pool.c.inc | 6 +- tcg/tci/tcg-target.c.inc | 2 +- MAINTAINERS | 2 + accel/tcg/trace-events | 2 +- qemu-options.hx | 7 + util/meson.build | 2 +- 63 files changed, 1017 insertions(+), 591 deletions(-) create mode 100644 include/qemu/cacheflush.h create mode 100644 util/cacheflush.c -- 2.25.1