[00/18] target/arm: Second slice of MVE implementation

This patchseries provides the second slice of the MVE implementation.
In this series:
 * fixes for bugs in a couple of the insns committed to upstream
   as part of the first slice
 * the logical immediate insns (including a preliminary refactoring
   to share the asimd_imm_const() decode between Neon, A64 and MVE)
 * some vector shifts
 * all the new MVE shift instructions which sit entirely within the
   non-coprocessor part of the encoding space and operate only on
   general purpose registers (either 32-bit shifts of one register,
   or 64-bit shifts of a register pair). These insns are not
   predicable and not subject to beatwise execution.
 * VADDLV (add long across vector)
 * VSHLC (shift left entire vector with carry in and out)

(I haven't yet got to the shift-vector-by-scalar-in-register
shift insns yet; those will be in some future patchset.)

This is a bit smaller than the first slice patchseries was, but
softfreeze is approaching and I wanted to give this the best chance of
getting through code review before then. (Not that it matters much if
it doesn't, it just means I would be carrying more patches locally
until we reopen for 6.2.)

thanks
-- PMM

Peter Maydell (18):
  target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
  target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
  target/arm: Make asimd_imm_const() public
  target/arm: Use asimd_imm_const for A64 decode
  target/arm: Use dup_const() instead of bitfield_replicate()
  target/arm: Implement MVE logical immediate insns
  target/arm: Implement MVE vector shift left by immediate insns
  target/arm: Implement MVE vector shift right by immediate insns
  target/arm: Implement MVE VSHLL
  target/arm: Implement MVE VSRI, VSLI
  target/arm: Implement MVE VSHRN, VRSHRN
  target/arm: Implement MVE saturating narrowing shifts
  target/arm: Implement MVE VSHLC
  target/arm: Implement MVE VADDLV
  target/arm: Implement MVE long shifts by immediate
  target/arm: Implement MVE long shifts by register
  target/arm: Implement MVE shifts by immediate
  target/arm: Implement MVE shifts by register

 target/arm/helper-mve.h     | 108 ++++++++
 target/arm/translate.h      |  41 +++
 target/arm/mve.decode       | 177 +++++++++++-
 target/arm/t32.decode       |  55 +++-
 target/arm/mve_helper.c     | 524 ++++++++++++++++++++++++++++++++++--
 target/arm/translate-a64.c  |  86 +-----
 target/arm/translate-mve.c  | 261 +++++++++++++++++-
 target/arm/translate-neon.c |  81 ------
 target/arm/translate.c      | 327 +++++++++++++++++++++-
 9 files changed, 1465 insertions(+), 195 deletions(-)

-- 
2.20.1

Patchew URL: https://patchew.org/QEMU/20210628135835.6690-1-peter.maydell@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20210628135835.6690-1-peter.maydell@linaro.org
Subject: [PATCH 00/18] target/arm: Second slice of MVE implementation

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20210628113047.462498-1-berrange@redhat.com -> patchew/20210628113047.462498-1-berrange@redhat.com
 * [new tag]         patchew/20210628135835.6690-1-peter.maydell@linaro.org -> patchew/20210628135835.6690-1-peter.maydell@linaro.org
Switched to a new branch 'test'
85b5d3e target/arm: Implement MVE shifts by register
33b8434 target/arm: Implement MVE shifts by immediate
e28665d target/arm: Implement MVE long shifts by register
bfa1b65 target/arm: Implement MVE long shifts by immediate
03ce1de target/arm: Implement MVE VADDLV
9131ded target/arm: Implement MVE VSHLC
37a01d1 target/arm: Implement MVE saturating narrowing shifts
86f6ee0 target/arm: Implement MVE VSHRN, VRSHRN
05463f1 target/arm: Implement MVE VSRI, VSLI
25969c7 target/arm: Implement MVE VSHLL
644c6a3 target/arm: Implement MVE vector shift right by immediate insns
c9d27a6 target/arm: Implement MVE vector shift left by immediate insns
96cef79 target/arm: Implement MVE logical immediate insns
829b634 target/arm: Use dup_const() instead of bitfield_replicate()
56573af target/arm: Use asimd_imm_const for A64 decode
a7f15a0 target/arm: Make asimd_imm_const() public
908a1ae target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
60ff08a target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation

=== OUTPUT BEGIN ===
1/18 Checking commit 60ff08a2237f (target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation)
2/18 Checking commit 908a1ae70d47 (target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH)
3/18 Checking commit a7f15a071127 (target/arm: Make asimd_imm_const() public)
4/18 Checking commit 56573af7e364 (target/arm: Use asimd_imm_const for A64 decode)
5/18 Checking commit 829b634182f9 (target/arm: Use dup_const() instead of bitfield_replicate())
6/18 Checking commit 96cef793eb97 (target/arm: Implement MVE logical immediate insns)
7/18 Checking commit c9d27a6b4f36 (target/arm: Implement MVE vector shift left by immediate insns)
8/18 Checking commit 644c6a3a67b6 (target/arm: Implement MVE vector shift right by immediate insns)
9/18 Checking commit 25969c777287 (target/arm: Implement MVE VSHLL)
10/18 Checking commit 05463f17e19b (target/arm: Implement MVE VSRI, VSLI)
WARNING: Block comments use a leading /* on a separate line
#70: FILE: target/arm/mve_helper.c:1264:
+            /*                                                          \

WARNING: Block comments use a leading /* on a separate line
#79: FILE: target/arm/mve_helper.c:1273:
+        /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */     \

total: 0 errors, 2 warnings, 80 lines checked

Patch 10/18 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/18 Checking commit 86f6ee0dc542 (target/arm: Implement MVE VSHRN, VRSHRN)
12/18 Checking commit 37a01d116824 (target/arm: Implement MVE saturating narrowing shifts)
13/18 Checking commit 9131dedb2193 (target/arm: Implement MVE VSHLC)
ERROR: spaces required around that '*' (ctx:WxV)
#95: FILE: target/arm/translate-mve.c:942:
+static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
                                                    ^

total: 1 errors, 0 warnings, 84 lines checked

Patch 13/18 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

14/18 Checking commit 03ce1decda5e (target/arm: Implement MVE VADDLV)
15/18 Checking commit bfa1b652a800 (target/arm: Implement MVE long shifts by immediate)
16/18 Checking commit e28665d91923 (target/arm: Implement MVE long shifts by register)
17/18 Checking commit 33b8434e3743 (target/arm: Implement MVE shifts by immediate)
18/18 Checking commit 85b5d3e63387 (target/arm: Implement MVE shifts by register)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20210628135835.6690-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
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