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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id u25-20020a62ed19000000b004f140515d56sm3318043pfh.46.2022.03.03.11.15.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 11:15:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 0/9] tcg: support 32-bit guest addresses as signed Date: Thu, 3 Mar 2022 09:15:42 -1000 Message-Id: <20220303191551.466631-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::630 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have 3 hosts that naturally produce sign-extended values, and have to work extra hard (with 1 or 2 insns) to produce the zero-extended address that we expect today. However, it's a simple matter of arithmetic for the middle-end to require sign-extended addresses instead. For user-only, we do have to be careful not to allow a guest object to wrap around the signed boundary, but that's fairly easily done. Tested with aarch64, as that's the best hw currently available. Only patch 6, for tcg/aarch64, is lacking review, which has been revised to include a AArch64LdstExt enum, per review. r~ Richard Henderson (9): tcg: Add TCG_TARGET_SIGNED_ADDR32 accel/tcg: Split out g2h_tlbe accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu accel/tcg: Add guest_base_signed_addr32 for user-only linux-user: Support TCG_TARGET_SIGNED_ADDR32 tcg/aarch64: Support TCG_TARGET_SIGNED_ADDR32 tcg/mips: Support TCG_TARGET_SIGNED_ADDR32 tcg/riscv: Support TCG_TARGET_SIGNED_ADDR32 tcg/loongarch64: Support TCG_TARGET_SIGNED_ADDR32 include/exec/cpu-all.h | 20 ++++++-- include/exec/cpu_ldst.h | 3 +- tcg/aarch64/tcg-target-sa32.h | 7 +++ tcg/arm/tcg-target-sa32.h | 1 + tcg/i386/tcg-target-sa32.h | 1 + tcg/loongarch64/tcg-target-sa32.h | 1 + tcg/mips/tcg-target-sa32.h | 9 ++++ tcg/ppc/tcg-target-sa32.h | 1 + tcg/riscv/tcg-target-sa32.h | 5 ++ tcg/s390x/tcg-target-sa32.h | 1 + tcg/sparc/tcg-target-sa32.h | 1 + tcg/tci/tcg-target-sa32.h | 1 + accel/tcg/cputlb.c | 36 +++++++++----- bsd-user/main.c | 4 ++ linux-user/elfload.c | 62 ++++++++++++++++++----- linux-user/main.c | 3 ++ tcg/tcg.c | 4 ++ tcg/aarch64/tcg-target.c.inc | 81 ++++++++++++++++++++++--------- tcg/loongarch64/tcg-target.c.inc | 15 +++--- tcg/mips/tcg-target.c.inc | 10 +--- tcg/riscv/tcg-target.c.inc | 8 +-- 21 files changed, 199 insertions(+), 75 deletions(-) create mode 100644 tcg/aarch64/tcg-target-sa32.h create mode 100644 tcg/arm/tcg-target-sa32.h create mode 100644 tcg/i386/tcg-target-sa32.h create mode 100644 tcg/loongarch64/tcg-target-sa32.h create mode 100644 tcg/mips/tcg-target-sa32.h create mode 100644 tcg/ppc/tcg-target-sa32.h create mode 100644 tcg/riscv/tcg-target-sa32.h create mode 100644 tcg/s390x/tcg-target-sa32.h create mode 100644 tcg/sparc/tcg-target-sa32.h create mode 100644 tcg/tci/tcg-target-sa32.h