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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 00/24] target/arm: 8 new features, A76 and N1 Date: Mon, 11 Apr 2022 17:33:02 -0700 Message-Id: <20220412003326.588530-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For v2, combine two previous patch sets and address comments. Patches lacking review: 03-target-arm-Move-cortex-impdef-sysregs-to-cpu_tcg..patch 04-target-arm-Update-qemu-system-arm-cpu-max-to-cort.patch 06-target-arm-Split-out-arm32_max_features.patch 12-target-arm-Add-minimal-RAS-registers.patch 14-target-arm-Implement-virtual-SError-exceptions.patch 20-target-arm-Enable-FEAT_CSV2_2-for-cpu-max.patch 23-target-arm-Define-cortex-a76.patch 24-target-arm-Define-neoverse-n1.patch r~ Richard Henderson (24): target/arm: Add isar predicates for FEAT_Debugv8p2 target/arm: Adjust definition of CONTEXTIDR_EL2 target/arm: Move cortex impdef sysregs to cpu_tcg.c target/arm: Update qemu-system-arm -cpu max to cortex-a57 target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max target/arm: Split out arm32_max_features target/arm: Annotate arm_max_initfn with FEAT identifiers target/arm: Use field names for manipulating EL2 and EL3 modes target/arm: Enable FEAT_Debugv8p2 for -cpu max target/arm: Enable FEAT_Debugv8p4 for -cpu max target/arm: Add isar_feature_{aa64,any}_ras target/arm: Add minimal RAS registers target/arm: Enable SCR and HCR bits for RAS target/arm: Implement virtual SError exceptions target/arm: Implement ESB instruction target/arm: Enable FEAT_RAS for -cpu max target/arm: Enable FEAT_IESB for -cpu max target/arm: Enable FEAT_CSV2 for -cpu max target/arm: Update ISAR fields for ARMv8.8 target/arm: Enable FEAT_CSV2_2 for -cpu max target/arm: Enable FEAT_CSV3 for -cpu max target/arm: Enable FEAT_DGH for -cpu max target/arm: Define cortex-a76 target/arm: Define neoverse-n1 docs/system/arm/emulation.rst | 10 + docs/system/arm/virt.rst | 2 + target/arm/cpu.h | 72 +++++++ target/arm/helper.h | 1 + target/arm/internals.h | 16 ++ target/arm/syndrome.h | 5 + target/arm/a32.decode | 16 +- target/arm/t32.decode | 18 +- hw/arm/sbsa-ref.c | 2 + hw/arm/virt.c | 2 + target/arm/cpu.c | 61 +++++- target/arm/cpu64.c | 349 +++++++++++++++++++--------------- target/arm/cpu_tcg.c | 228 ++++++++++++++++------ target/arm/helper.c | 246 +++++++++++++++++++++++- target/arm/op_helper.c | 43 +++++ target/arm/translate-a64.c | 18 ++ target/arm/translate.c | 23 +++ 17 files changed, 866 insertions(+), 246 deletions(-)