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[0/6] target/arm: Fix v8 AArch32 RAZ ID regs; implement FEAT_ETS

Message ID 20220819110052.2942289-1-peter.maydell@linaro.org
Headers show
Series target/arm: Fix v8 AArch32 RAZ ID regs; implement FEAT_ETS | expand

Message

Peter Maydell Aug. 19, 2022, 11 a.m. UTC 
The main aim of this patchset is to implement FEAT_ETS.
FEAT_ETS provides tighter guarantees on some memory orderings
involving translation table walks that permit guest code to
skip the context-synchronization event they would otherwise
need to do after a TLB maintenance operation. QEMU already
provides the tighter guarantees this feature requires, so
all we need to do is advertise it in the ID registers...

...except that it turns out that for AArch32 this is done
in ID_MMFR5, which is a new-in-v8.6 register that we don't
implement yet. So we need to provide it. And while I was
doing that I noticed that we accidentally forgot to
implement a big chunk of the "reserved for future ID
registers, must RAZ" cp15 space for v8 AArch32. So the
big bit of the patchset is sorting that out :-)

thanks
-- PMM

Peter Maydell (6):
  target/arm: Make cpregs 0, c0, c{3-15}, {0-7} correctly RAZ in v8
  target/arm: Sort KVM reads of AArch32 ID registers into encoding order
  target/arm: Implement ID_MMFR5
  target/arm: Implement ID_DFR1
  target/arm: Advertise FEAT_ETS for '-cpu max'
  target/arm: Add missing space in comment

 docs/system/arm/emulation.rst |  1 +
 target/arm/cpu.h              |  2 +
 target/arm/cpu64.c            |  1 +
 target/arm/cpu_tcg.c          |  6 ++-
 target/arm/helper.c           | 69 +++++++++++++++++++++++++++++++----
 target/arm/kvm64.c            |  8 +++-
 6 files changed, 77 insertions(+), 10 deletions(-)

Comments

Richard Henderson Aug. 23, 2022, 9:48 p.m. UTC | #1 
On 8/19/22 04:00, Peter Maydell wrote:
> The main aim of this patchset is to implement FEAT_ETS.
> FEAT_ETS provides tighter guarantees on some memory orderings
> involving translation table walks that permit guest code to
> skip the context-synchronization event they would otherwise
> need to do after a TLB maintenance operation. QEMU already
> provides the tighter guarantees this feature requires, so
> all we need to do is advertise it in the ID registers...
> 
> ...except that it turns out that for AArch32 this is done
> in ID_MMFR5, which is a new-in-v8.6 register that we don't
> implement yet. So we need to provide it. And while I was
> doing that I noticed that we accidentally forgot to
> implement a big chunk of the "reserved for future ID
> registers, must RAZ" cp15 space for v8 AArch32. So the
> big bit of the patchset is sorting that out :-)

Thanks, queued to target-arm.next.


r~