[v7,00/18] tcg: CPUTLBEntryFull and TARGET_TB_PCREL

Message ID	20221004141051.110653-1-richard.henderson@linaro.org
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Series	tcg: CPUTLBEntryFull and TARGET_TB_PCREL \| expand [v7,00/18] tcg: CPUTLBEntryFull and TARGET_TB_PCREL [v7,01/18] cpu: cache CPUClass in CPUState for hot code paths [v7,02/18] hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs [v7,03/18] cputlb: used cached CPUClass in our hot-paths [v7,04/18] accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull [v7,05/18] accel/tcg: Drop addr member from SavedIOTLB [v7,06/18] accel/tcg: Suppress auto-invalidate in probe_access_internal [v7,07/18] accel/tcg: Introduce probe_access_full [v7,08/18] accel/tcg: Introduce tlb_set_page_full [v7,09/18] include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA [v7,10/18] accel/tcg: Remove PageDesc code_bitmap [v7,11/18] accel/tcg: Use bool for page_find_alloc [v7,12/18] accel/tcg: Use DisasContextBase in plugin_gen_tb_start [v7,13/18] accel/tcg: Do not align tb->page_addr[0] [v7,14/18] accel/tcg: Inline tb_flush_jmp_cache [v7,15/18] include/hw/core: Create struct CPUJumpCache [v7,16/18] hw/core: Add CPUClass.get_pc [v7,17/18] accel/tcg: Introduce tb_pc and log_pc [v7,18/18] accel/tcg: Introduce TARGET_TB_PCREL

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20221004141051.110653-1-richard.henderson@linaro.org

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Subject: [PATCH v7 00/18] tcg: CPUTLBEntryFull and TARGET_TB_PCREL
Date: Tue,  4 Oct 2022 07:10:33 -0700
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Series

tcg: CPUTLBEntryFull and TARGET_TB_PCREL | expand

Message

Richard Henderson Oct. 4, 2022, 2:10 p.m. UTC

Changes for v7:
  * Added stub for --disable-tcg (stsquad)
  * Re-worded the commit for patch 13 (stsquad)
  * Split out some more helpers around ifdefs in patch 18 (stsquad)

Patches needing review:
  13-accel-tcg-Do-not-align-tb-page_addr-0.patch
  17-accel-tcg-Introduce-tb_pc-and-log_pc.patch
  18-accel-tcg-Introduce-TARGET_TB_PCREL.patch


r~


Alex Bennée (3):
  cpu: cache CPUClass in CPUState for hot code paths
  hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs
  cputlb: used cached CPUClass in our hot-paths

Richard Henderson (15):
  accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull
  accel/tcg: Drop addr member from SavedIOTLB
  accel/tcg: Suppress auto-invalidate in probe_access_internal
  accel/tcg: Introduce probe_access_full
  accel/tcg: Introduce tlb_set_page_full
  include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA
  accel/tcg: Remove PageDesc code_bitmap
  accel/tcg: Use bool for page_find_alloc
  accel/tcg: Use DisasContextBase in plugin_gen_tb_start
  accel/tcg: Do not align tb->page_addr[0]
  accel/tcg: Inline tb_flush_jmp_cache
  include/hw/core: Create struct CPUJumpCache
  hw/core: Add CPUClass.get_pc
  accel/tcg: Introduce tb_pc and log_pc
  accel/tcg: Introduce TARGET_TB_PCREL

 accel/tcg/internal.h                    |  10 +
 accel/tcg/tb-hash.h                     |   1 +
 accel/tcg/tb-jmp-cache.h                |  65 ++++++
 include/exec/cpu-common.h               |   1 +
 include/exec/cpu-defs.h                 |  48 ++++-
 include/exec/exec-all.h                 |  75 ++++++-
 include/exec/plugin-gen.h               |   7 +-
 include/hw/core/cpu.h                   |  28 ++-
 include/qemu/typedefs.h                 |   2 +
 include/tcg/tcg.h                       |   2 +-
 accel/stubs/tcg-stub.c                  |   4 +
 accel/tcg/cpu-exec.c                    |  80 ++++----
 accel/tcg/cputlb.c                      | 259 ++++++++++++++----------
 accel/tcg/plugin-gen.c                  |  22 +-
 accel/tcg/translate-all.c               | 214 +++++++++-----------
 accel/tcg/translator.c                  |   2 +-
 cpu.c                                   |   9 +-
 hw/core/cpu-common.c                    |   3 +-
 hw/core/cpu-sysemu.c                    |   5 +-
 plugins/core.c                          |   2 +-
 target/alpha/cpu.c                      |   9 +
 target/arm/cpu.c                        |  17 +-
 target/arm/mte_helper.c                 |  14 +-
 target/arm/sve_helper.c                 |   4 +-
 target/arm/translate-a64.c              |   2 +-
 target/avr/cpu.c                        |  10 +-
 target/cris/cpu.c                       |   8 +
 target/hexagon/cpu.c                    |  10 +-
 target/hppa/cpu.c                       |  12 +-
 target/i386/cpu.c                       |   9 +
 target/i386/tcg/tcg-cpu.c               |   2 +-
 target/loongarch/cpu.c                  |  11 +-
 target/m68k/cpu.c                       |   8 +
 target/microblaze/cpu.c                 |  10 +-
 target/mips/cpu.c                       |   8 +
 target/mips/tcg/exception.c             |   2 +-
 target/mips/tcg/sysemu/special_helper.c |   2 +-
 target/nios2/cpu.c                      |   9 +
 target/openrisc/cpu.c                   |  10 +-
 target/ppc/cpu_init.c                   |   8 +
 target/riscv/cpu.c                      |  17 +-
 target/rx/cpu.c                         |  10 +-
 target/s390x/cpu.c                      |   8 +
 target/s390x/tcg/mem_helper.c           |   4 -
 target/sh4/cpu.c                        |  12 +-
 target/sparc/cpu.c                      |  10 +-
 target/tricore/cpu.c                    |  11 +-
 target/xtensa/cpu.c                     |   8 +
 tcg/tcg.c                               |   8 +-
 trace/control-target.c                  |   2 +-
 50 files changed, 739 insertions(+), 355 deletions(-)
 create mode 100644 accel/tcg/tb-jmp-cache.h