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[46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 00/57] tcg: Simplify calls to load/store helpers Date: Mon, 24 Apr 2023 06:40:08 +0100 Message-Id: <20230424054105.1579315-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org v1: https://lore.kernel.org/qemu-devel/20230408024314.3357414-1-richard.henderson@linaro.org/ v2: https://lore.kernel.org/qemu-devel/20230411010512.5375-1-richard.henderson@linaro.org/ There are several changes to the load/store helpers coming, and making sure that those changes are properly reflected across all of the backends was harrowing. I have gone back and restarted by hoisting the code out of the backends and into tcg.c. We already have all of the parameters for the host function call abi for "normal" helpers, we simply need to apply that to the load/store slow path. The major change for v3 is prepare_host_addr(), as a merge of several routines and some code from tcg_out_qemu_{ld,st}. This is pulled back from my (working) atomicity patch set, making i128 easier. The patches are many, but take heart: the diffstat is -523. :-) About 1/3 of the patches have been reviewed in some form. r~ Richard Henderson (57): tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64 tcg/mips: Conditionalize tcg_out_exts_i32_i64 tcg/i386: Conditionalize tcg_out_extu_i32_i64 tcg: Introduce tcg_out_movext2 tcg/i386: Rationalize args to tcg_out_qemu_{ld,st} tcg/i386: Generalize multi-part load overlap test tcg/i386: Introduce HostAddress tcg/i386: Drop r0+r1 local variables from tcg_out_tlb_load tcg/i386: Introduce tcg_out_testi tcg/i386: Introduce prepare_host_addr tcg/i386: Use indexed addressing for softmmu fast path tcg/aarch64: Rationalize args to tcg_out_qemu_{ld,st} tcg/aarch64: Introduce HostAddress tcg/aarch64: Introduce prepare_host_addr tcg/arm: Rationalize args to tcg_out_qemu_{ld,st} tcg/arm: Introduce HostAddress tcg/arm: Introduce prepare_host_addr tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld,st} tcg/loongarch64: Introduce HostAddress tcg/loongarch64: Introduce prepare_host_addr tcg/mips: Rationalize args to tcg_out_qemu_{ld,st} tcg/mips: Introduce prepare_host_addr tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st} tcg/ppc: Introduce HostAddress tcg/ppc: Introduce prepare_host_addr tcg/riscv: Require TCG_TARGET_REG_BITS == 64 tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st} tcg/riscv: Introduce prepare_host_addr tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st} tcg/s390x: Introduce HostAddress tcg/s390x: Introduce prepare_host_addr tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st} tcg: Move TCGLabelQemuLdst to tcg.c tcg: Replace REG_P with arg_loc_reg_p tcg: Introduce arg_slot_stk_ofs tcg: Widen helper_*_st[bw]_mmu val arguments tcg: Add routines for calling slow-path helpers tcg/i386: Convert tcg_out_qemu_ld_slow_path tcg/i386: Convert tcg_out_qemu_st_slow_path tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path tcg/arm: Convert tcg_out_qemu_{ld,st}_slow_path tcg/loongarch64: Convert tcg_out_qemu_{ld,st}_slow_path tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path tcg/ppc: Convert tcg_out_qemu_{ld,st}_slow_path tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_path tcg/s390x: Convert tcg_out_qemu_{ld,st}_slow_path tcg/loongarch64: Simplify constraints on qemu_ld/st tcg/mips: Remove MO_BSWAP handling tcg/mips: Reorg tlb load within prepare_host_addr tcg/mips: Simplify constraints on qemu_ld/st tcg/ppc: Reorg tcg_out_tlb_read tcg/ppc: Adjust constraints on qemu_ld/st tcg/ppc: Remove unused constraints A, B, C, D tcg/riscv: Simplify constraints on qemu_ld/st tcg/s390x: Use ALGFR in constructing softmmu host address tcg/s390x: Simplify constraints on qemu_ld/st include/tcg/tcg-ldst.h | 10 +- tcg/loongarch64/tcg-target-con-set.h | 2 - tcg/loongarch64/tcg-target-con-str.h | 1 - tcg/mips/tcg-target-con-set.h | 13 +- tcg/mips/tcg-target-con-str.h | 2 - tcg/mips/tcg-target.h | 4 +- tcg/ppc/tcg-target-con-set.h | 11 +- tcg/ppc/tcg-target-con-str.h | 6 - tcg/riscv/tcg-target-con-set.h | 8 - tcg/riscv/tcg-target-con-str.h | 1 - tcg/riscv/tcg-target.h | 22 +- tcg/s390x/tcg-target-con-set.h | 2 - tcg/s390x/tcg-target-con-str.h | 1 - tcg/tcg-internal.h | 4 - accel/tcg/cputlb.c | 6 +- tcg/tcg.c | 582 +++++++++++++++- tcg/aarch64/tcg-target.c.inc | 363 +++++----- tcg/arm/tcg-target.c.inc | 726 ++++++++------------ tcg/i386/tcg-target.c.inc | 707 +++++++++----------- tcg/loongarch64/tcg-target.c.inc | 376 +++++------ tcg/mips/tcg-target.c.inc | 946 ++++++++------------------- tcg/ppc/tcg-target.c.inc | 637 ++++++++---------- tcg/riscv/tcg-target.c.inc | 508 +++++--------- tcg/s390x/tcg-target.c.inc | 393 +++++------ tcg/sparc64/tcg-target.c.inc | 8 +- tcg/tcg-ldst.c.inc | 14 - 26 files changed, 2415 insertions(+), 2938 deletions(-)