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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v7-20020a05600c214700b003f72a15301csm594952wml.2.2023.06.02.08.52.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:52:25 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 00/20] target/arm: Convert exception, system, loads and stores to decodetree Date: Fri, 2 Jun 2023 16:52:03 +0100 Message-Id: <20230602155223.2040685-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This patchseries does more of the conversion of the A64 decoder to decodetree. It covers the exception-generation, system, load and store instructions. After this the remaining legacy decoder pieces are: * data-processing (register) * data-processing (SIMD) * data-processing (floating-point) I plan to take a break from conversion after this series to work on FEAT_MOPS, but want to come back to the dp-register parts for this release cycle. The FP/SIMD stuff is a bigger job and I'm inclined to leave it for the moment. I include the LDSMIN/LDSMAX bugfix as patch 1 to avoid a conflict later. Speaking of conflicts, this is going to conflict with RTH's LSE2 series, which I expect to get in to the tree first, but I'm hoping the rebase of this series won't be too painful. thanks -- PMM Peter Maydell (20): target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics target/arm: Convert hint instruction space to decodetree target/arm: Convert barrier insns to decodetree target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree target/arm: Convert MSR (immediate) to decodetree target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree target/arm: Convert exception generation instructions to decodetree target/arm: Convert load/store exclusive and ordered to decodetree target/arm: Convert LDXP, STXP, CASP, CAS to decodetree target/arm: Convert load reg (literal) group to decodetree target/arm: Convert load/store-pair to decodetree target/arm: Convert ld/st reg+imm9 insns to decodetree target/arm: Convert LDR/STR with 12-bit immediate to decodetree target/arm: Convert LDR/STR reg+reg to decodetree target/arm: Convert atomic memory ops to decodetree target/arm: Convert load (pointer auth) insns to decodetree target/arm: Convert LDAPR/STLR (imm) to decodetree target/arm: Convert load/store (multiple structures) to decodetree target/arm: Convert load/store single structure to decodetree target/arm: Convert load/store tags insns to decodetree target/arm/tcg/a64.decode | 406 ++++ target/arm/tcg/translate-a64.c | 3183 ++++++++++++++------------------ 2 files changed, 1801 insertions(+), 1788 deletions(-)