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X-Received: by 2002:a2e:9807:0:b0:2b6:e2aa:8fc2 with SMTP id a7-20020a2e9807000000b002b6e2aa8fc2mr11593798ljj.46.1689077696411; Tue, 11 Jul 2023 05:14:56 -0700 (PDT) Received: from m1x-phil.lan ([176.187.194.156]) by smtp.gmail.com with ESMTPSA id o16-20020a1709062e9000b00992ea405a79sm1072478eji.166.2023.07.11.05.14.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 11 Jul 2023 05:14:56 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Daniel Henrique Barboza , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH-for-8.2 v3 00/16] target/riscv: Allow building without TCG (KVM-only so far) Date: Tue, 11 Jul 2023 14:14:37 +0200 Message-Id: <20230711121453.59138-1-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22e; envelope-from=philmd@linaro.org; helo=mail-lj1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org v3: Rebased on master (commit 94d68c1136, merge tag 'pull-riscv-to-apply-20230710-1') Philippe Mathieu-Daudé (16): target/riscv: Remove unuseful KVM stubs target/riscv: Remove unused 'instmap.h' header in translate.c target/riscv: Restrict sysemu specific header to user emulation target/riscv: Restrict 'rv128' machine to TCG accelerator target/riscv: Move sysemu-specific files to target/riscv/sysemu/ target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu target/riscv: Move TCG-specific files to target/riscv/tcg/ target/riscv: Move TCG-specific cpu_get_tb_cpu_state() to tcg/cpu.c target/riscv: Expose some 'trigger' prototypes from debug.c target/riscv: Extract TCG-specific code from debug.c target/riscv: Move sysemu-specific debug files to target/riscv/sysemu/ target/riscv: Expose riscv_cpu_pending_to_irq() from cpu_helper.c target/riscv: Move TCG/sysemu-specific code to tcg/sysemu/cpu_helper.c target/riscv: Move sysemu-specific code to sysemu/cpu_helper.c target/riscv: Restrict TCG-specific prototype declarations gitlab-ci.d/crossbuilds: Add KVM riscv64 cross-build jobs target/riscv/cpu.h | 27 +- target/riscv/internals.h | 4 + target/riscv/{ => sysemu}/debug.h | 6 + target/riscv/{ => sysemu}/instmap.h | 0 target/riscv/{ => sysemu}/kvm_riscv.h | 0 target/riscv/{ => sysemu}/pmp.h | 0 target/riscv/{ => sysemu}/pmu.h | 0 target/riscv/{ => sysemu}/time_helper.h | 0 target/riscv/{ => tcg}/XVentanaCondOps.decode | 0 target/riscv/{ => tcg}/insn16.decode | 0 target/riscv/{ => tcg}/insn32.decode | 0 target/riscv/{ => tcg}/xthead.decode | 0 hw/riscv/virt.c | 2 +- target/riscv/cpu.c | 35 +- target/riscv/cpu_helper.c | 1692 +---------------- target/riscv/csr.c | 6 +- target/riscv/{ => sysemu}/arch_dump.c | 0 target/riscv/sysemu/cpu_helper.c | 863 +++++++++ target/riscv/{ => sysemu}/debug.c | 153 +- target/riscv/{ => sysemu}/kvm-stub.c | 0 target/riscv/{ => sysemu}/kvm.c | 4 +- target/riscv/{ => sysemu}/machine.c | 0 target/riscv/{ => sysemu}/monitor.c | 0 target/riscv/{ => sysemu}/pmp.c | 0 target/riscv/{ => sysemu}/pmu.c | 0 target/riscv/{ => sysemu}/riscv-qmp-cmds.c | 0 target/riscv/{ => sysemu}/time_helper.c | 0 target/riscv/{ => tcg}/bitmanip_helper.c | 0 target/riscv/tcg/cpu.c | 98 + target/riscv/{ => tcg}/crypto_helper.c | 0 target/riscv/{ => tcg}/fpu_helper.c | 0 target/riscv/{ => tcg}/m128_helper.c | 0 target/riscv/{ => tcg}/op_helper.c | 0 target/riscv/tcg/sysemu/cpu_helper.c | 765 ++++++++ target/riscv/tcg/sysemu/debug.c | 165 ++ target/riscv/tcg/tcg-stub.c | 31 + target/riscv/{ => tcg}/translate.c | 1 - target/riscv/{ => tcg}/vector_helper.c | 0 target/riscv/{ => tcg}/zce_helper.c | 0 .gitlab-ci.d/crossbuilds.yml | 8 + target/riscv/meson.build | 33 +- target/riscv/sysemu/meson.build | 13 + target/riscv/tcg/meson.build | 22 + target/riscv/tcg/sysemu/meson.build | 4 + 44 files changed, 2038 insertions(+), 1894 deletions(-) rename target/riscv/{ => sysemu}/debug.h (96%) rename target/riscv/{ => sysemu}/instmap.h (100%) rename target/riscv/{ => sysemu}/kvm_riscv.h (100%) rename target/riscv/{ => sysemu}/pmp.h (100%) rename target/riscv/{ => sysemu}/pmu.h (100%) rename target/riscv/{ => sysemu}/time_helper.h (100%) rename target/riscv/{ => tcg}/XVentanaCondOps.decode (100%) rename target/riscv/{ => tcg}/insn16.decode (100%) rename target/riscv/{ => tcg}/insn32.decode (100%) rename target/riscv/{ => tcg}/xthead.decode (100%) rename target/riscv/{ => sysemu}/arch_dump.c (100%) create mode 100644 target/riscv/sysemu/cpu_helper.c rename target/riscv/{ => sysemu}/debug.c (83%) rename target/riscv/{ => sysemu}/kvm-stub.c (100%) rename target/riscv/{ => sysemu}/kvm.c (99%) rename target/riscv/{ => sysemu}/machine.c (100%) rename target/riscv/{ => sysemu}/monitor.c (100%) rename target/riscv/{ => sysemu}/pmp.c (100%) rename target/riscv/{ => sysemu}/pmu.c (100%) rename target/riscv/{ => sysemu}/riscv-qmp-cmds.c (100%) rename target/riscv/{ => sysemu}/time_helper.c (100%) rename target/riscv/{ => tcg}/bitmanip_helper.c (100%) create mode 100644 target/riscv/tcg/cpu.c rename target/riscv/{ => tcg}/crypto_helper.c (100%) rename target/riscv/{ => tcg}/fpu_helper.c (100%) rename target/riscv/{ => tcg}/m128_helper.c (100%) rename target/riscv/{ => tcg}/op_helper.c (100%) create mode 100644 target/riscv/tcg/sysemu/cpu_helper.c create mode 100644 target/riscv/tcg/sysemu/debug.c create mode 100644 target/riscv/tcg/tcg-stub.c rename target/riscv/{ => tcg}/translate.c (99%) rename target/riscv/{ => tcg}/vector_helper.c (100%) rename target/riscv/{ => tcg}/zce_helper.c (100%) create mode 100644 target/riscv/sysemu/meson.build create mode 100644 target/riscv/tcg/meson.build create mode 100644 target/riscv/tcg/sysemu/meson.build