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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d1804b6b1sm32323945ad.189.2024.10.16.12.31.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2024 12:31:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, zhiwei_liu@linux.alibaba.com Subject: [PATCH v6 00/14] tcg/riscv: Add support for vector Date: Wed, 16 Oct 2024 12:31:26 -0700 Message-ID: <20241016193140.2206352-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Introduce support for the RISC-V vector extension in the TCG backend. v5: https://lore.kernel.org/qemu-devel/20241007025700.47259-1-zhiwei_liu@linux.alibaba.com/ Changes for v6: - Fix problem with TB overflow restart wrt the constant pool. - Fix vsetivli disassembly. - Change set_vtype to precompute all instructions. - Extract one element before comparison in tcg_out_dupi_vec. - Extract one element before comparison in tcg_target_const_match. - Drop 'vm' parameter from most tcg_out_opc_* functions. - Add tcg_out_opc_vv_vi and accept K constants for operations which have .v.i instructions. - Do not expand cmp_vec early. - Fix expansion of rotls_vec. I've tested this on cfarm95, a banana pi bpi-f3 with 256-bit rvv-1.0, with qemu-aarch64 and some vectorized test cases. Barring further comment, I plan to include this in a PR at the end of the week. r~ Huang Shiyuan (1): tcg/riscv: Add basic support for vector Richard Henderson (3): tcg: Reset data_gen_ptr correctly disas/riscv: Fix vsetivli disassembly tcg/riscv: Accept constant first argument to sub_vec TANG Tiancheng (10): util: Add RISC-V vector extension probe in cpuinfo tcg/riscv: Implement vector mov/dup{m/i} tcg/riscv: Add support for basic vector opcodes tcg/riscv: Implement vector cmp/cmpsel ops tcg/riscv: Implement vector neg ops tcg/riscv: Implement vector sat/mul ops tcg/riscv: Implement vector min/max ops tcg/riscv: Implement vector shi/s/v ops tcg/riscv: Implement vector roti/v/x ops tcg/riscv: Enable native vector support for TCG host disas/riscv.h | 2 +- host/include/riscv/host/cpuinfo.h | 2 + include/tcg/tcg.h | 6 + tcg/riscv/tcg-target-con-set.h | 9 + tcg/riscv/tcg-target-con-str.h | 3 + tcg/riscv/tcg-target.h | 78 ++- tcg/riscv/tcg-target.opc.h | 12 + disas/riscv.c | 2 +- tcg/tcg.c | 2 +- util/cpuinfo-riscv.c | 24 +- tcg/riscv/tcg-target.c.inc | 994 +++++++++++++++++++++++++++--- 11 files changed, 1011 insertions(+), 123 deletions(-) create mode 100644 tcg/riscv/tcg-target.opc.h Signed-off-by: Huang Shiyuan