From patchwork Fri Oct 25 14:12:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 838359 Delivered-To: patch@linaro.org Received: by 2002:adf:e287:0:b0:37d:45d0:187 with SMTP id v7csp308557wri; Fri, 25 Oct 2024 07:17:42 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW9A2igGQuIlQBMLxNYSTFAJApm74Y1bthEiQmihQ5BRtQHh0yPM9tC+9dj7ymMCmI4y95L1A==@linaro.org X-Google-Smtp-Source: AGHT+IFzDOZMFFKoCGiImPpXGg+R05e4MTmZvFhjXz1Fr66Efibo9Eb4BjyhJJZVFGK1QLkhs5Qg X-Received: by 2002:a05:6808:164a:b0:3e6:2f8c:317a with SMTP id 5614622812f47-3e62f8c31bamr3760178b6e.2.1729865861885; Fri, 25 Oct 2024 07:17:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1729865861; cv=none; d=google.com; s=arc-20240605; b=Cy/yXnLWM6BsByx5JPJvyEDsIidFNv6IgAuyCd8A238FiahQyAgUV34ZwbfcoeN4j0 8sZnAZ4eNt1WIEw5/Yb3IbpyWjJ5gq+uuGRFUncWTlR09F8zvjeUiiCB1kYBgmxMN7QQ avV+0tJysZMuQalKai9PikTkg0pmfbhTl487OHroXImvvIVrjzkXza3DzBC3oZC9E/km qExpEnjgjO1NOv1nz8nLe8dLE0MIXSGuth2a/nm6QLeec3jHb0oI2iq0C00NqNENGhYW cwbZAcoBxkiOFDRI7qOUMFX/QaCDFQGMpzQ4EPZ2RTLVspqvFQ5K7EL8AH5OcqrRtUxs 7U3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:dkim-signature; bh=FpcQQjq66hc60h15t5XebYBsiuHjNC9wWkvbtWI3lC4=; fh=s3exyCP09+w24wCP1HiLef86vTkU/bIdRqnQs5WcC58=; b=M015nc3tkLTvbinUPfxGJRN7oU4ZbdgW27AwokILZLp2MZ1du8UrVXNVHn8RUpqzQp gupdwlWPt0gEG41I5OixE1tPVF7Y2cjV2izCJNrXkgV5bugWJZhip3OLoBH/TAcAcesD 2bKCZe5ye/scL8tkX0OqU5GXOOV/IUpesN5LNgJ3cHXgQAfUEc05rMKmtJOIz/Q2NK50 +31qTdnUwxoIFmcWBrQQCoCxR4OWNj6wnDbEGFvKGQ5Zjb9TZegbabj3eMPVwsS4cGrY vJnKmeyGF5i8Nd7QVY85I/Hc+kHkfmi5TnqYFPl58K7RKYjviwwpCwemM/fHelHJSipc rSKQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Bt4+d1Rn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ada2fe7eead31-4a8c53464bfsi322614137.502.2024.10.25.07.17.41 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Oct 2024 07:17:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Bt4+d1Rn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t4L3p-00040t-Tj; Fri, 25 Oct 2024 10:13:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t4L3l-0003wo-Pj for qemu-devel@nongnu.org; Fri, 25 Oct 2024 10:13:01 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t4L3i-0007lE-89 for qemu-devel@nongnu.org; Fri, 25 Oct 2024 10:13:01 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4315eac969aso14573155e9.1 for ; Fri, 25 Oct 2024 07:12:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1729865576; x=1730470376; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=FpcQQjq66hc60h15t5XebYBsiuHjNC9wWkvbtWI3lC4=; b=Bt4+d1RniQy9YgpP3WXQGCvc+eQJOoxdns7iAdki09E63yR25ZgSlwsvLL8T5A+gYc YH2Z4vIwRKnaHGpEeKGnEby6RVKDjb5im55N58zbUwi0YN64nmK7P2ouv3mBqYQqtcWh bOa/jpXZ/qufE9BmzvEayhR8ttTsXC3qsqhweIoXI+nQRe/rOl84AiNBzr/Pg948WJv/ kpVdDsaduIBYBsC1U2pkNQTPrPyuAQWqYtwYJSf4vHQ8SsyZljIHeC2BsOIan8dkGAW3 5BNlH4H2rD8oTBDtTflzsTR+wVqQYI2cl6kwQANrNexyw3udn+SGy4j7ULKNfoC6Wjmv vm/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729865576; x=1730470376; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=FpcQQjq66hc60h15t5XebYBsiuHjNC9wWkvbtWI3lC4=; b=cAUc3qxDaC7KQGvMKLmojqitTYIzqgOJx0eAKD3ELKPM086mvkxFBGLcgD/2416NEN Gern69Fe9Z8boDBKs3dT+2OaOSo9FmMXtNic2gTXFoibBfH8BzSaB5omWJvtWQ+xanrA JV9Mv44C0nt2gPWlpxT5Sy9k8A0Tvl1PMdc/nXwDESv3fcwolO7ECKpKN9V44RtUrgZX iTyzNbq2Xq/+lTSSv6SFvpue9PIVgWnManbs71dIaqMtKKdRvjgo5WQZnf2msJ6eWnfF p0+RZQmMweCFU3FVdimqXuTYkCvy4Hdgkefqo60hBVe0epF2cYNNoLUMCEgc8azjzuIu gJDg== X-Forwarded-Encrypted: i=1; AJvYcCUzycRSxY2gCRjZfEUOa8p+ftEWTpr2cS4G0Vv3O8kficV6FHJwEXOIzYR2O9LexBPRvKhKPnSJAC2s@nongnu.org X-Gm-Message-State: AOJu0YzN17fXkf6NFKZgY/bbd2PE9EWHz32DCI2qyhH97lMUiHHQifoV 4cC9tK9xT3Hl+sivR9/J/EnMGoT8FoP/9IdyZJXU/4i7YtTNj0U1oovFltXdfM0= X-Received: by 2002:a05:600c:35c3:b0:431:4a82:97f2 with SMTP id 5b1f17b1804b1-4318b5a42edmr44666555e9.6.1729865576232; Fri, 25 Oct 2024 07:12:56 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b57b051sm50104535e9.42.2024.10.25.07.12.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 07:12:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Song Gao , Eduardo Habkost , "Edgar E. Iglesias" , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 00/21] softfloat: Set 2-NaN propagation rule in float_status, not at compile time Date: Fri, 25 Oct 2024 15:12:33 +0100 Message-Id: <20241025141254.2141506-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org IEEE 758 does not define a fixed rule for which NaN to pick as the result if both operands of a 2-operand operation are NaNs. As a result different architectures have ended up with different rules for propagating NaNs. QEMU currently hardcodes the NaN propagation logic into the binary, because pickNaN() has an ifdef ladder for different targets. We want to make the propagation rule instead be selectable at runtime, because: * this will let us have multiple targets in one QEMU binary * the Arm FEAT_AFP architectural feature includes letting the guest select a NaN propagation rule at runtime * x86 specifies different propagation rules for x87 FPU ops and for SSE ops, and specifying the rule in the float_status would let us emulate this, instead of wrongly using the x87 rules everywhere * xtensa allows selection of NaN propagation rule at runtime; currently we implement this with the use_first_nan flag which is only used by xtensa; providing a general facility will let us remove this limited-purpose handling This series switches pickNaN away from the ifdef ladder. Instead targets must always set a 2-NaN propagation rule via the new set_float_2nan_prop_rule(), unless they are using default_nan_mode. Patch 1 implements this in core softfloat (with a transitional fallback to "use the old ifdef ladder logic" if the target doesn't specify the propagation rule). Then subsequent patches convert all the targets to set the rule explicitly. The final patch then removes the remnants of the transitional logic. I have included a couple of minor fixes for sparc, xtensa, m68k. This is intended as a no-behaviour-change patchset, so although there are a few places where I have noticed that the current behaviour is not correct I have left these as TODO comments. A summary of those TODOs and other oddities I have noticed but not tried to tackle is: * hppa really ought to implement a CPU reset method * alpha also doesn't implement CPU reset * ppc sets tininess_before_rounding on fp_status but not on vec_status, so its behaviour there will vary between guest instructions; unclear to me if this is intended * x86 should set the float_2nan_prop_ab rule on env->sse_status (and maybe env->mmx_status, though 3DNow! insns don't handle NaNs in a documented way anyway) * alpha never had a case in the ifdef ladder so it uses the x87 propagation rule. It ought to use float_2nan_prop_ba. * openrisc didn't have an ifdef and also uses the x87 rule; this is probably wrong but I couldn't find anything documenting what it actually does * rx didn't have an ifdef and also uses the x87 rule; again, probably wrong The next stage after this patchset, obviously, is to do the same thing with pickNaNMulAdd(). That is a little trickier because currently we ask it to do two things: * handle the "infinity * zero + NaN" corner case * pick a NaN when more than one operand is a NaN My intention is to separate these out so that targets specify both separately. This gives more orthogonality (e.g. Arm, MIPS with !snan_bit_is_one and loongarch64 all have the same "prefer SNaN over QNaN, prefer C over A over B" NaN selection logic but they have different ideas about the infzero case). (Once pickNaNMulAdd() is converted we will be able to remove the current xtensa-specific use_first_nan flag.) thanks -- PMM Peter Maydell (21): softfloat: Allow 2-operand NaN propagation rule to be set at runtime tests/fp: Explicitly set 2-NaN propagation rule target/arm: Explicitly set 2-NaN propagation rule target/mips: Explicitly set 2-NaN propagation rule target/loongarch: Explicitly set 2-NaN propagation rule target/hppa: Explicitly set 2-NaN propagation rule target/s390x: Explicitly set 2-NaN propagation rule target/ppc: Explicitly set 2-NaN propagation rule target/m68k: Explicitly set 2-NaN propagation rule target/m68k: Initialize float_status fields in gdb set/get functions target/sparc: Move cpu_put_fsr(env, 0) call to reset target/sparc: Explicitly set 2-NaN propagation rule target/xtensa: Factor out calls to set_use_first_nan() target/xtensa: Explicitly set 2-NaN propagation rule target/i386: Set 2-NaN propagation rule explicitly target/alpha: Explicitly set 2-NaN propagation rule target/microblaze: Move setting of float rounding mode to reset target/microblaze: Explicitly set 2-NaN propagation rule target/openrisc: Explicitly set 2-NaN propagation rule target/rx: Explicitly set 2-NaN propagation rule softfloat: Remove fallback rule from pickNaN() include/fpu/softfloat-helpers.h | 11 +++ include/fpu/softfloat-types.h | 38 ++++++++ target/i386/cpu.h | 3 + target/mips/fpu_helper.h | 22 +++++ target/xtensa/cpu.h | 6 ++ linux-user/arm/nwfpe/fpa11.c | 18 ++++ target/alpha/cpu.c | 11 +++ target/arm/cpu.c | 25 +++-- target/hppa/fpu_helper.c | 6 ++ target/i386/cpu.c | 4 + target/i386/tcg/fpu_helper.c | 40 ++++++++ target/loongarch/tcg/fpu_helper.c | 1 + target/m68k/cpu.c | 16 +++ target/m68k/fpu_helper.c | 1 + target/m68k/helper.c | 4 +- target/microblaze/cpu.c | 10 +- target/mips/cpu.c | 2 +- target/mips/msa.c | 17 ++++ target/openrisc/cpu.c | 6 ++ target/ppc/cpu_init.c | 8 ++ target/rx/cpu.c | 7 ++ target/s390x/cpu.c | 1 + target/sparc/cpu.c | 10 +- target/sparc/fop_helper.c | 10 +- target/xtensa/cpu.c | 2 +- target/xtensa/fpu_helper.c | 35 ++++--- tests/fp/fp-bench.c | 2 + tests/fp/fp-test-log2.c | 1 + tests/fp/fp-test.c | 2 + fpu/softfloat-specialize.c.inc | 156 +++++++++++------------------- 30 files changed, 346 insertions(+), 129 deletions(-)