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Show patches with
: Submitter =
Richard Henderson
| 22843 patches
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Delegate
------
Nobody
andy.doan@linaro.org
andy.doan@linaro.org
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Patch
Series
S/W/F
Date
Submitter
Delegate
State
[RISU,v2,07/13] contrib/generate_all: Do not rely on ag
ELF and Sparc64 support
-
-
-
2024-05-26
Richard Henderson
New
[RISU,v2,06/13] risugen: Add sparc64 support
ELF and Sparc64 support
-
-
-
2024-05-26
Richard Henderson
New
[RISU,v2,05/13] risugen: Be explicit about print destinations
ELF and Sparc64 support
-
-
-
2024-05-26
Richard Henderson
New
[RISU,v2,04/13] risu: Add initial sparc64 support
ELF and Sparc64 support
-
-
-
2024-05-26
Richard Henderson
New
[RISU,v2,03/13] Introduce host_context_t
ELF and Sparc64 support
-
-
-
2024-05-26
Richard Henderson
New
[RISU,v2,02/13] Build elf test cases instead of raw binaries
ELF and Sparc64 support
-
-
-
2024-05-26
Richard Henderson
New
[RISU,v2,01/13] risu: Allow use of ELF test files
ELF and Sparc64 support
-
-
-
2024-05-26
Richard Henderson
New
[v2,67/67] target/arm: Convert FCSEL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
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-
-
2024-05-24
Richard Henderson
Superseded
[v2,66/67] target/arm: Convert FMADD, FMSUB, FNMADD, FNMSUB to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
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-
-
2024-05-24
Richard Henderson
Superseded
[v2,65/67] target/arm: Convert SQDMULH, SQRDMULH to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,64/67] target/arm: Tidy SQDMULH, SQRDMULH (vector)
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,63/67] target/arm: Convert MLA, MLS to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,62/67] target/arm: Convert MUL, PMUL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,61/67] target/arm: Convert SABA, SABD, UABA, UABD to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,60/67] target/arm: Convert SMAX, SMIN, UMAX, UMIN to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,59/67] target/arm: Convert SRHADD, URHADD to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,58/67] target/arm: Convert SRHADD, URHADD to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,57/67] target/arm: Convert SHSUB, UHSUB to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,56/67] target/arm: Convert SHSUB, UHSUB to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,55/67] target/arm: Convert SHADD, UHADD to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,54/67] target/arm: Convert SHADD, UHADD to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,53/67] target/arm: Use TCG_COND_TSTNE in gen_cmtst_vec
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,52/67] target/arm: Use TCG_COND_TSTNE in gen_cmtst_{i32, i64}
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,51/67] target/arm: Convert CMGT, CMHI, CMGE, CMHS, CMTST, CMEQ to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,50/67] target/arm: Convert ADD, SUB (vector) to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,49/67] target/arm: Convert SQRSHL, UQRSHL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,48/67] target/arm: Convert SQRSHL and UQRSHL (register) to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,47/67] target/arm: Convert SQSHL, UQSHL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,46/67] target/arm: Convert SQSHL and UQSHL (register) to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,45/67] target/arm: Convert SRSHL, URSHL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
New
[v2,44/67] target/arm: Convert SRSHL and URSHL (register) to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,43/67] target/arm: Convert SSHL, USHL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
New
[v2,42/67] target/arm: Convert SUQADD, USQADD to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,41/67] target/arm: Convert SQADD, SQSUB, UQADD, UQSUB to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,40/67] target/arm: Inline scalar SQADD, UQADD, SQSUB, UQSUB
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,39/67] target/arm: Inline scalar SUQADD and USQADD
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,38/67] target/arm: Convert SUQADD and USQADD to gvec
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
New
[v2,37/67] target/arm: Improve vector UQADD, UQSUB, SQADD, SQSUB
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,36/67] target/arm: Convert disas_simd_3same_logic to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,35/67] target/arm: Convert FMLAL, FMLSL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,34/67] target/arm: Use gvec for neon pmax, pmin
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,33/67] target/arm: Convert SMAXP, SMINP, UMAXP, UMINP to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
New
[v2,32/67] target/arm: Use gvec for neon padd
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,31/67] target/arm: Convert ADDP to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,30/67] target/arm: Use gvec for neon faddp, fmaxp, fminp
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,29/67] target/arm: Convert FMAXP, FMINP, FMAXNMP, FMINNMP to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
New
[v2,28/67] target/arm: Convert FADDP to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,27/67] target/arm: Convert FRECPS, FRSQRTS to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,26/67] target/arm: Convert FABD to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,25/67] target/arm: Convert FCMEQ, FCMGE, FCMGT, FACGE, FACGT to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,24/67] target/arm: Convert FMLA, FMLS to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,23/67] target/arm: Convert FNMUL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,22/67] target/arm: Expand vfp neg and abs inline
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
New
[v2,21/67] target/arm: Introduce vfp_load_reg16
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,20/67] target/arm: Convert FMAX, FMIN, FMAXNM, FMINNM to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,19/67] target/arm: Convert FADD, FSUB, FDIV, FMUL to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
New
[v2,18/67] target/arm: Convert FMULX to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
New
[v2,17/67] target/arm: Convert Advanced SIMD copy to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,16/67] target/arm: Convert XAR to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,15/67] target/arm: Convert Cryptographic 3-register, imm2 to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,14/67] target/arm: Convert Cryptographic 4-register to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,13/67] target/arm: Convert Cryptographic 2-register SHA512 to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,12/67] target/arm: Convert Cryptographic 3-register SHA512 to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,11/67] target/arm: Convert Cryptographic 2-register SHA to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,10/67] target/arm: Convert Cryptographic 3-register SHA to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,09/67] target/arm: Convert Cryptographic AES to decodetree
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,08/67] target/arm: Split out gengvec64.c
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
New
[v2,07/67] target/arm: Split out gengvec.c
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
New
[v2,06/67] target/arm: Verify sz=0 for Advanced SIMD scalar pairwise (fp16)
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,05/67] target/arm: Fix decode of FMOV (hp) vs MOVI
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,04/67] target/arm: Zero-extend writeback for fp16 FCVTZS (scalar, integer)
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,03/67] target/arm: Reject incorrect operands to PLD, PLDW, PLI
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
New
[v2,02/67] target/arm: Use PLD, PLDW, PLI not NOP for t32
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
Superseded
[v2,01/67] target/arm: Add neoverse-n1 to qemu-arm (DO NOT MERGE)
target/arm: Convert a64 advsimd to decodetree (part 1)
-
-
-
2024-05-24
Richard Henderson
New
[PULL,5/5] accel/tcg: Init tb size and icount before plugin_gen_tb_end
[PULL,1/5] tcg: Introduce TCG_TARGET_HAS_tst_vec
-
-
-
2024-05-23
Richard Henderson
Accepted
[PULL,4/5] tcg/arm: Support TCG_TARGET_HAS_tst_vec
[PULL,1/5] tcg: Introduce TCG_TARGET_HAS_tst_vec
-
-
-
2024-05-23
Richard Henderson
New
[PULL,3/5] tcg/aarch64: Support TCG_TARGET_HAS_tst_vec
[PULL,1/5] tcg: Introduce TCG_TARGET_HAS_tst_vec
-
-
-
2024-05-23
Richard Henderson
New
[PULL,2/5] tcg: Expand TCG_COND_TST* if not TCG_TARGET_HAS_tst_vec
[PULL,1/5] tcg: Introduce TCG_TARGET_HAS_tst_vec
-
-
-
2024-05-23
Richard Henderson
Accepted
[PULL,1/5] tcg: Introduce TCG_TARGET_HAS_tst_vec
[PULL,1/5] tcg: Introduce TCG_TARGET_HAS_tst_vec
-
-
-
2024-05-23
Richard Henderson
Accepted
[PULL,0/5] tcg patch queue
-
-
-
2024-05-23
Richard Henderson
New
[RISU,4/4] contrib/generate_all: Do not rely on ag
risugen/arm: Convert to use assembly
-
-
-
2024-05-22
Richard Henderson
Superseded
[RISU,3/4] risugen/arm: Switch to thumb mode only once
risugen/arm: Convert to use assembly
-
-
-
2024-05-22
Richard Henderson
New
[RISU,2/4] risugen/arm: Fill general regs with 64-bit random data
risugen/arm: Convert to use assembly
-
-
-
2024-05-22
Richard Henderson
New
[RISU,1/4] risugen/arm: Convert to use assembly
risugen/arm: Convert to use assembly
-
-
-
2024-05-22
Richard Henderson
New
[RISU,v2,8/8] sparc64: Add VIS1 instructions
ELF and Sparc64 support
-
-
-
2024-05-22
Richard Henderson
Superseded
[RISU,v2,7/8] sparc64: Add a few logical insns
ELF and Sparc64 support
-
-
-
2024-05-22
Richard Henderson
Superseded
[RISU,v2,6/8] risugen: Add sparc64 support
ELF and Sparc64 support
-
-
-
2024-05-22
Richard Henderson
Superseded
[RISU,v2,5/8] risugen: Be explicit about print destinations
ELF and Sparc64 support
-
-
-
2024-05-22
Richard Henderson
Superseded
[RISU,v2,4/8] risu: Add initial sparc64 support
ELF and Sparc64 support
-
-
-
2024-05-22
Richard Henderson
Superseded
[RISU,v2,3/8] Introduce host_context_t
ELF and Sparc64 support
-
-
-
2024-05-22
Richard Henderson
Superseded
[RISU,v2,2/8] Build elf test cases instead of raw binaries
ELF and Sparc64 support
-
-
-
2024-05-22
Richard Henderson
Superseded
[RISU,v2,1/8] risu: Allow use of ELF test files
ELF and Sparc64 support
-
-
-
2024-05-22
Richard Henderson
Superseded
accel/tcg: Init tb size and icount before plugin_gen_tb_end
accel/tcg: Init tb size and icount before plugin_gen_tb_end
-
-
-
2024-05-21
Richard Henderson
Superseded
[v3,28/28] target/i386: Pass host pointer and size to cpu_x86_{xsave, xrstor}
linux-user/i386: Properly align signal frame
-
-
-
2024-05-15
Richard Henderson
Superseded
[v3,27/28] target/i386: Pass host pointer and size to cpu_x86_{fxsave, fxrstor}
linux-user/i386: Properly align signal frame
-
-
-
2024-05-15
Richard Henderson
Superseded
[v3,26/28] target/i386: Pass host pointer and size to cpu_x86_{fsave, frstor}
linux-user/i386: Properly align signal frame
-
-
-
2024-05-15
Richard Henderson
Superseded
[v3,25/28] target/i386: Convert do_xrstor to X86Access
linux-user/i386: Properly align signal frame
-
-
-
2024-05-15
Richard Henderson
Superseded
[v3,24/28] target/i386: Convert do_xsave to X86Access
linux-user/i386: Properly align signal frame
-
-
-
2024-05-15
Richard Henderson
Superseded
[v3,23/28] target/i386: Honor xfeatures in xrstor_sigcontext
linux-user/i386: Properly align signal frame
-
-
-
2024-05-15
Richard Henderson
Superseded
[v3,22/28] linux-user/i386: Fix allocation and alignment of fp state
linux-user/i386: Properly align signal frame
-
-
-
2024-05-15
Richard Henderson
Superseded
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