Show patches with: Submitter = Richard Henderson       |   22808 patches
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Patch Series S/W/F Date Submitter Delegate State
[v2,15/45] target/hppa: Use umax in do_ibranch_priv target/hppa: Misc improvements --- 2024-05-13 Richard Henderson Superseded
[v2,14/45] target/hppa: Add space argument to do_ibranch target/hppa: Misc improvements --- 2024-05-13 Richard Henderson Superseded
[v2,13/45] target/hppa: Add space arguments to install_iaq_entries target/hppa: Misc improvements --- 2024-05-13 Richard Henderson Superseded
[v2,12/45] target/hppa: Add IASQ entries to DisasContext target/hppa: Misc improvements --- 2024-05-13 Richard Henderson Superseded
[v2,11/45] target/hppa: Simplify TB end target/hppa: Misc improvements --- 2024-05-13 Richard Henderson Superseded
[v2,10/45] target/hppa: Skip nullified insns in unconditional dbranch path target/hppa: Misc improvements --- 2024-05-13 Richard Henderson Superseded
[v2,09/45] target/hppa: Delay computation of IAQ_Next target/hppa: Misc improvements --- 2024-05-13 Richard Henderson Superseded
[v2,08/45] target/hppa: Add install_link target/hppa: Misc improvements --- 2024-05-13 Richard Henderson Superseded
[v2,07/45] target/hppa: Add install_iaq_entries target/hppa: Misc improvements --- 2024-05-13 Richard Henderson Superseded
[v2,06/45] target/hppa: Use CF_BP_PAGE instead of cpu_breakpoint_test target/hppa: Misc improvements --- 2024-05-13 Richard Henderson Superseded
[v2,05/45] target/hppa: Allow prior nullification in do_ibranch target/hppa: Misc improvements --- 2024-05-13 Richard Henderson Superseded
[v2,04/45] target/hppa: Pass displacement to do_dbranch target/hppa: Misc improvements --- 2024-05-13 Richard Henderson Superseded
[v2,03/45] target/hppa: Move constant destination check into use_goto_tb target/hppa: Misc improvements --- 2024-05-13 Richard Henderson Superseded
[v2,02/45] target/hppa: Use hppa_form_gva_psw in hppa_cpu_get_pc target/hppa: Misc improvements --- 2024-05-13 Richard Henderson Superseded
[v2,01/45] target/hppa: Move cpu_get_tb_cpu_state out of line target/hppa: Misc improvements --- 2024-05-13 Richard Henderson Superseded
[17/17] Build elf test cases instead of raw binaries RISU misc updates --- 2024-05-11 Richard Henderson Superseded
[16/17] configure: Enable loongarch64 RISU misc updates --- 2024-05-11 Richard Henderson New
[15/17] risu: Allow use of ELF test files RISU misc updates --- 2024-05-11 Richard Henderson New
[14/17] aarch64: Use bool for sve_{z,p}reg_is_eq RISU misc updates --- 2024-05-11 Richard Henderson New
[13/17] Use bool for reginfo_is_eq RISU misc updates --- 2024-05-11 Richard Henderson New
[12/17] aarch64: Trivial SME test RISU misc updates --- 2024-05-11 Richard Henderson New
[11/17] aarch64: Add support for ZA storage RISU misc updates --- 2024-05-11 Richard Henderson New
[10/17] aarch64: Tidy reginfo dumping ahead of ZA state RISU misc updates --- 2024-05-11 Richard Henderson New
[09/17] ppc64: Clean up reginfo_dump RISU misc updates --- 2024-05-11 Richard Henderson New
[08/17] ppc64: Simplify reginfo_is_eq RISU misc updates --- 2024-05-11 Richard Henderson New
[07/17] ppc64: Compare all bits of CCR RISU misc updates --- 2024-05-11 Richard Henderson New
[06/17] ppc64: Clean register values in reginfo_init RISU misc updates --- 2024-05-11 Richard Henderson New
[05/17] Remove return value from reginfo_dump RISU misc updates --- 2024-05-11 Richard Henderson New
[04/17] Add --fulldump and --diffdup options RISU misc updates --- 2024-05-11 Richard Henderson New
[03/17] Standardize reginfo_dump_mismatch printing RISU misc updates --- 2024-05-11 Richard Henderson New
[02/17] Fix load_image error check for mmap RISU misc updates --- 2024-05-11 Richard Henderson New
[01/17] ppc64: Fix <sys/user.h> include order RISU misc updates --- 2024-05-11 Richard Henderson New
tcg/loongarch64: Fill out tcg_out_{ld,st} for vector regs tcg/loongarch64: Fill out tcg_out_{ld,st} for vector regs --- 2024-05-10 Richard Henderson Superseded
gitlab: Update msys2-64bit runner tags gitlab: Update msys2-64bit runner tags --- 2024-05-07 Richard Henderson Accepted
[PULL,9/9] gitlab: Streamline ubuntu-22.04-s390x [PULL,1/9] tcg: Add write_aofs to GVecGen3i --- 2024-05-07 Richard Henderson Accepted
[PULL,8/9] gitlab: Drop --static from s390x linux-user build [PULL,1/9] tcg: Add write_aofs to GVecGen3i --- 2024-05-07 Richard Henderson Accepted
[PULL,7/9] gitlab: Drop --disable-libssh from ubuntu-22.04-s390x.yml [PULL,1/9] tcg: Add write_aofs to GVecGen3i --- 2024-05-07 Richard Henderson Accepted
[PULL,6/9] target/sh4: Update DisasContextBase.insn_start [PULL,1/9] tcg: Add write_aofs to GVecGen3i --- 2024-05-07 Richard Henderson Accepted
[PULL,5/9] accel/tcg: Introduce CF_BP_PAGE [PULL,1/9] tcg: Add write_aofs to GVecGen3i --- 2024-05-07 Richard Henderson New
[PULL,4/9] tcg/optimize: Optimize setcond with zmask [PULL,1/9] tcg: Add write_aofs to GVecGen3i --- 2024-05-07 Richard Henderson Accepted
[PULL,3/9] tcg/i386: Optimize setcond of TST{EQ,NE} with 0xffffffff [PULL,1/9] tcg: Add write_aofs to GVecGen3i --- 2024-05-07 Richard Henderson Accepted
[PULL,2/9] tcg/i386: Simplify immediate 8-bit logical vector shifts [PULL,1/9] tcg: Add write_aofs to GVecGen3i --- 2024-05-07 Richard Henderson Accepted
[PULL,1/9] tcg: Add write_aofs to GVecGen3i [PULL,1/9] tcg: Add write_aofs to GVecGen3i --- 2024-05-07 Richard Henderson Accepted
[PULL,0/9] tcg + misc patch queue --- 2024-05-07 Richard Henderson New
gitlab: Rename ubuntu-22.04-s390x-all to *-system gitlab: Rename ubuntu-22.04-s390x-all to *-system --- 2024-05-06 Richard Henderson New
gitlab: Drop --static from s390x linux-user build gitlab: Drop --static from s390x linux-user build --- 2024-05-06 Richard Henderson Superseded
target/sh4: Update DisasContextBase.insn_start target/sh4: Update DisasContextBase.insn_start --- 2024-05-06 Richard Henderson Superseded
[57/57] target/arm: Convert SQDMULH, SQRDMULH to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[56/57] target/arm: Tidy SQDMULH, SQRDMULH (vector) target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[55/57] target/arm: Convert MLA, MLS to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[54/57] target/arm: Convert MUL, PMUL to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[53/57] target/arm: Convert SABA, SABD, UABA, UABD to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[52/57] target/arm: Convert SMAX, SMIN, UMAX, UMIN to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[51/57] target/arm: Convert SRHADD, URHADD to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[50/57] target/arm: Convert SRHADD, URHADD to gvec target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[49/57] target/arm: Convert SHSUB, UHSUB to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[48/57] target/arm: Convert SHSUB, UHSUB to gvec target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[47/57] target/arm: Convert SHADD, UHADD to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[46/57] target/arm: Convert SHADD, UHADD to gvec target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[45/57] target/arm: Use TCG_COND_TSTNE in gen_cmtst_{i32,i64} target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[44/57] target/arm: Convert CMGT, CMHI, CMGE, CMHS, CMTST, CMEQ to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[43/57] target/arm: Convert ADD, SUB (vector) to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[42/57] target/arm: Convert SQRSHL, UQRSHL to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[41/57] target/arm: Convert SQRSHL and UQRSHL (register) to gvec target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[40/57] target/arm: Convert SQSHL, UQSHL to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[39/57] target/arm: Convert SQSHL and UQSHL (register) to gvec target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[38/57] target/arm: Convert SRSHL, URSHL to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[37/57] target/arm: Convert SRSHL and URSHL (register) to gvec target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[36/57] target/arm: Convert SSHL, USHL to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[35/57] target/arm: Convert SUQADD, USQADD to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[34/57] target/arm: Convert SQADD, SQSUB, UQADD, UQSUB to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[33/57] target/arm: Inline scalar SQADD, UQADD, SQSUB, UQSUB target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[32/57] target/arm: Inline scalar SUQADD and USQADD target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[31/57] target/arm: Convert SUQADD and USQADD to gvec target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[30/57] target/arm: Improve vector UQADD, UQSUB, SQADD, SQSUB target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[29/57] target/arm: Convert disas_simd_3same_logic to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[28/57] target/arm: Convert FMLAL, FMLSL to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[27/57] target/arm: Use gvec for neon pmax, pmin target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[26/57] target/arm: Convert SMAXP, SMINP, UMAXP, UMINP to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[25/57] target/arm: Use gvec for neon padd target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[24/57] target/arm: Convert ADDP to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[23/57] target/arm: Use gvec for neon faddp, fmaxp, fminp target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[22/57] target/arm: Convert FMAXP, FMINP, FMAXNMP, FMINNMP to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[21/57] target/arm: Convert FADDP to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[20/57] target/arm: Convert FRECPS, FRSQRTS to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[19/57] target/arm: Convert FABD to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[18/57] target/arm: Convert FCMEQ, FCMGE, FCMGT, FACGE, FACGT to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[17/57] target/arm: Convert FMLA, FMLS to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[16/57] target/arm: Convert FNMUL to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[15/57] target/arm: Expand vfp neg and abs inline target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[14/57] target/arm: Convert FMAX, FMIN, FMAXNM, FMINNM to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[13/57] target/arm: Convert FADD, FSUB, FDIV, FMUL to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[12/57] target/arm: Convert FMULX to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[11/57] target/arm: Convert Advanced SIMD copy to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[10/57] target/arm: Convert XAR to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[09/57] target/arm: Convert Cryptographic 3-register, imm2 to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[08/57] target/arm: Convert Cryptographic 4-register to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[07/57] target/arm: Convert Cryptographic 2-register SHA512 to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[06/57] target/arm: Convert Cryptographic 3-register SHA512 to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
[05/57] target/arm: Convert Cryptographic 2-register SHA to decodetree target/arm: Convert a64 advsimd to decodetree (part 1) --- 2024-05-06 Richard Henderson Superseded
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