Show patches with: State = Action Required       |    Archived = No       |   21450 patches
« 1 2 ... 26 27 28 … 214 215 »
Patch Series S/W/F Date Submitter Delegate State
[PULL,35/37] target/riscv: Introduce helper_set_rounding_mode_chkfrm Untitled series #198566 --- 2023-01-20 Alistair Francis New
[PULL,34/37] tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst Untitled series #198566 --- 2023-01-20 Alistair Francis New
[PULL,v3,24/43] target/riscv: Set pc_succ_insn for !rvc illegal insn Untitled series #197135 --- 2023-01-06 Alistair Francis New
[PULL,v3,04/43] tcg/riscv: Fix base register for user-only qemu_ld/st Untitled series #197135 --- 2023-01-06 Alistair Francis New
[PULL,v3,03/43] tcg/riscv: Fix reg overlap case in tcg_out_addsub2 Untitled series #197135 --- 2023-01-06 Alistair Francis New
[PULL,v3,02/43] tcg/riscv: Fix range matched by TCG_CT_CONST_M12 Untitled series #197135 --- 2023-01-06 Alistair Francis New
[PULL,v2,03/22] docs/system: clean up code escape for riscv virt platform Untitled series #187804 --- 2022-09-27 Alistair Francis New
[PULL,1/1] linux-user/riscv: Align signal frame to 16 bytes [PULL,1/1] linux-user/riscv: Align signal frame to 16 bytes --- 2022-08-01 Alistair Francis New
[PULL,v2,04/19] target/riscv: Minimize the calls to decode_save_opc Untitled series #180079 --- 2022-07-03 Alistair Francis New
[PULL,v2,03/19] target/riscv: Remove generate_exception_mtval Untitled series #180079 --- 2022-07-03 Alistair Francis New
[PULL,v2,02/19] target/riscv: Set env->bins in gen_exception_illegal Untitled series #180079 --- 2022-07-03 Alistair Francis New
[PULL,v2,17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults Untitled series #173457 --- 2022-04-22 Alistair Francis New
[PULL,2/2] meson.build: Merge riscv32 and riscv64 cpu family Untitled series #160940 --- 2021-11-17 Alistair Francis New
[PULL,22/33] target/riscv: Compute mstatus.sd on demand Untitled series #160136 --- 2021-10-22 Alistair Francis New
[PULL,21/33] target/riscv: Use riscv_csrrw_debug for cpu_dump Untitled series #160136 --- 2021-10-22 Alistair Francis New
[PULL,20/33] target/riscv: Use gen_shift*_per_ol for RVB, RVI Untitled series #160136 --- 2021-10-22 Alistair Francis New
[PULL,19/33] target/riscv: Use gen_unary_per_ol for RVB Untitled series #160136 --- 2021-10-22 Alistair Francis New
[PULL,18/33] target/riscv: Adjust trans_rev8_32 for riscv64 Untitled series #160136 --- 2021-10-22 Alistair Francis New
[PULL,17/33] target/riscv: Use gen_arith_per_ol for RVM Untitled series #160136 --- 2021-10-22 Alistair Francis New
[PULL,16/33] target/riscv: Replace DisasContext.w with DisasContext.ol Untitled series #160136 --- 2021-10-22 Alistair Francis New
[PULL,15/33] target/riscv: Replace is_32bit with get_xl/get_xlen Untitled series #160136 --- 2021-10-22 Alistair Francis New
[PULL,14/33] target/riscv: Properly check SEW in amo_op Untitled series #160136 --- 2021-10-22 Alistair Francis New
[PULL,13/33] target/riscv: Use REQUIRE_64BIT in amo_check64 Untitled series #160136 --- 2021-10-22 Alistair Francis New
[PULL,12/33] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Untitled series #160136 --- 2021-10-22 Alistair Francis New
[PULL,11/33] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Untitled series #160136 --- 2021-10-22 Alistair Francis New
[PULL,10/33] target/riscv: Split misa.mxl and misa.ext Untitled series #160136 --- 2021-10-22 Alistair Francis New
[PULL,09/33] target/riscv: Create RISCVMXL enumeration Untitled series #160136 --- 2021-10-22 Alistair Francis New
[PULL,08/33] target/riscv: Move cpu_get_tb_cpu_state out of line Untitled series #160136 --- 2021-10-22 Alistair Francis New
[PULL,33/33] target/riscv: Use {get,dest}_gpr for RVV Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,32/33] target/riscv: Tidy trans_rvh.c.inc Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,31/33] target/riscv: Use {get,dest}_gpr for RVD Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,30/33] target/riscv: Use {get,dest}_gpr for RVF Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,29/33] target/riscv: Use gen_shift_imm_fn for slli_uw Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,28/33] target/riscv: Use {get,dest}_gpr for RVA Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,27/33] target/riscv: Reorg csr instructions Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,26/33] target/riscv: Fix hgeie, hgeip Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,25/33] target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,24/33] target/riscv: Use {get, dest}_gpr for integer load/store Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,23/33] target/riscv: Use get_gpr in branches Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,22/33] target/riscv: Use extracts for sraiw and srliw Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,21/33] target/riscv: Use DisasExtend in shift operations Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,20/33] target/riscv: Add DisasExtend to gen_unary Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,19/33] target/riscv: Move gen_* helpers for RVB Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,18/33] target/riscv: Move gen_* helpers for RVM Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,17/33] target/riscv: Use gen_arith for mulh and mulhu Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,16/33] target/riscv: Remove gen_arith_div* Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,15/33] target/riscv: Add DisasExtend to gen_arith* Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,14/33] target/riscv: Introduce DisasExtend and new helpers Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,13/33] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,12/33] target/riscv: Clean up division helpers Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,11/33] tests/tcg/riscv64: Add test for division Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,10/33] target/riscv: Use tcg_constant_* Untitled series #155777 --- 2021-09-01 Alistair Francis New
[PULL,06/33] hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv() Untitled series #155777 --- 2021-09-01 Alistair Francis New
[v1,1/1] hw/intc/ibex_plic: Clear the claim register when read [v1,1/1] hw/intc/ibex_plic: Clear the claim register when read --- 2020-11-06 Alistair Francis New
[v4,4/5] target/riscv: Remove the hyp load and store functions [v4,1/5] target/riscv: Add a virtualised MMU Mode --- 2020-11-04 Alistair Francis New
[v4,1/5] target/riscv: Add a virtualised MMU Mode [v4,1/5] target/riscv: Add a virtualised MMU Mode --- 2020-11-04 Alistair Francis New
[v3,4/7] target/riscv: Remove the HS_TWO_STAGE flag [v3,1/7] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit --- 2020-11-03 Alistair Francis New
[v1,1/1] linux-user/syscall: Fix missing target_to_host_timespec64() check [v1,1/1] linux-user/syscall: Fix missing target_to_host_timespec64() check --- 2020-11-03 Alistair Francis New
[PULL,v2,19/19] target/riscv/csr.c : add space before the open parenthesis '(' Untitled series #75168 --- 2020-11-03 Alistair Francis New
[PULL,v2,11/19] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules Untitled series #75168 --- 2020-11-03 Alistair Francis New
[PULL,v2,10/19] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support Untitled series #75168 --- 2020-11-03 Alistair Francis New
[PULL,v2,08/19] target/riscv: Add sifive_plic vmstate Untitled series #75168 --- 2020-11-03 Alistair Francis New
[PULL,v2,06/19] target/riscv: Add H extension state description Untitled series #75168 --- 2020-11-03 Alistair Francis New
[PULL,18/18] hw/riscv: microchip_pfsoc: Hook the I2C1 controller riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,17/18] hw/riscv: microchip_pfsoc: Correct DDR memory map riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,16/18] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,15/18] hw/riscv: microchip_pfsoc: Connect the SYSREG module riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,14/18] hw/misc: Add Microchip PolarFire SoC SYSREG module support riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,13/18] hw/riscv: microchip_pfsoc: Connect the IOSCB module riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,12/18] hw/misc: Add Microchip PolarFire SoC IOSCB module support riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,09/18] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,07/18] target/riscv: Add V extension state description riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,05/18] target/riscv: Add PMP state description riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,04/18] target/riscv: Add basic vmstate description of CPU riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,03/18] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,02/18] hw/riscv: virt: Allow passing custom DTB riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[PULL,01/18] hw/riscv: sifive_u: Allow passing custom DTB riscv-to-apply queue --- 2020-10-29 Alistair Francis New
[v2,5/5] target/riscv: Split the Hypervisor execute load helpers Fix the Hypervisor access functions --- 2020-10-28 Alistair Francis New
[v2,4/5] target/riscv: Remove the hyp load and store functions Fix the Hypervisor access functions --- 2020-10-28 Alistair Francis New
[v2,2/5] target/riscv: Set the virtualised MMU mode when doing hyp accesses Fix the Hypervisor access functions --- 2020-10-28 Alistair Francis New
[v2,1/5] target/riscv: Add a virtualised MMU Mode Fix the Hypervisor access functions --- 2020-10-28 Alistair Francis New
[v1,16/16] target/riscv: Consolidate *statush registers RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,15/16] target/riscv: Convert the get/set_field() to support 64-bit values RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,14/16] target/riscv: cpu: Set XLEN independently from target RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,13/16] target/riscv: csr: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,12/16] target/riscv: cpu_helper: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,11/16] target/riscv: cpu: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,10/16] target/riscv: Specify the XLEN for CPUs RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,09/16] target/riscv: Add a riscv_cpu_is_32bit() helper function RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,08/16] target/riscv: fpu_helper: Match function defs in HELPER macros RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,07/16] hw/riscv: sifive_u: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,06/16] hw/riscv: spike: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,05/16] hw/riscv: virt: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,04/16] hw/riscv: boot: Remove compile time XLEN checks RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,03/16] riscv: virt: Remove target macro conditionals RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,02/16] riscv: spike: Remove target macro conditionals RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[v1,01/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU RISC-V: Start to remove xlen preprocess --- 2020-10-23 Alistair Francis New
[PULL,12/12] hw/misc/sifive_u_otp: Add backend drive support riscv-to-apply queue --- 2020-10-23 Alistair Francis New
[PULL,11/12] hw/misc/sifive_u_otp: Add write function and write-once protection riscv-to-apply queue --- 2020-10-23 Alistair Francis New
[PULL,10/12] target/riscv: raise exception to HS-mode at get_physical_address riscv-to-apply queue --- 2020-10-23 Alistair Francis New
« 1 2 ... 26 27 28 … 214 215 »