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Show patches with
: Series =
target-arm queue
| Archived =
No
| 24 patches
Series
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Delegate
------
Nobody
andy.doan@linaro.org
andy.doan@linaro.org
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Patch
Series
S/W/F
Date
Submitter
Delegate
State
[PULL,24/24] target/arm: Only implement doubles if the FPU supports them
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Not Applicable
[PULL,23/24] target/arm: Fix typos in trans function prototypes
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Accepted
[PULL,22/24] target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Accepted
[PULL,21/24] target/arm: Stop using deprecated functions in NEON_2RM_VCVT_F32_F16
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Accepted
[PULL,20/24] target/arm: stop using deprecated functions in NEON_2RM_VCVT_F16_F32
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Accepted
[PULL,19/24] target/arm: Stop using cpu_F0s in Neon VCVT fixed-point ops
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Accepted
[PULL,18/24] target/arm: Stop using cpu_F0s for Neon f32/s32 VCVT
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Accepted
[PULL,17/24] target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Accepted
[PULL,16/24] target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US]
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Accepted
[PULL,15/24] target/arm: Stop using cpu_F0s for NEON_2RM_VRINT*
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Accepted
[PULL,14/24] target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_F
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Accepted
[PULL,13/24] target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Accepted
[PULL,12/24] target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Accepted
[PULL,11/24] target/arm: Move vfp_expand_imm() to translate.[ch]
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Not Applicable
[PULL,10/24] hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Accepted
[PULL,09/24] hw/intc/arm_gicv3: Fix decoding of ID register range
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Accepted
[PULL,08/24] hw/arm: Correctly disable FPU/DSP for some ARMSSE-based boards
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Not Applicable
[PULL,07/24] hw/arm/armv7m: Forward "vfp" and "dsp" properties to CPU
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Not Applicable
[PULL,06/24] target/arm: Allow M-profile CPUs to disable the DSP extension via CPU property
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Not Applicable
[PULL,05/24] target/arm: Allow VFP and Neon to be disabled via a CPU property
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Not Applicable
[PULL,04/24] hw/arm/boot: Honour image size field in AArch64 Image format kernels
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Accepted
[PULL,03/24] hw/arm/boot: Avoid placing the initrd on top of the kernel
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Accepted
[PULL,02/24] hw/arm/boot: Diagnose layouts that put initrd or DTB off the end of RAM
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Accepted
[PULL,01/24] hw/arm/boot: Don't assume RAM starts at address zero
target-arm queue
-
-
-
2019-06-17
Peter Maydell
Accepted